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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter' H. X! j% S2 D! ^% a
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance+ T0 E( [$ }- m! Y; q
on par with commercially available PLLs, while being relatively simple to design and use as1 T. S0 ^1 ^- P1 F& y" Y
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
* b' j6 @! Y+ q/ s, Mnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In5 i8 a" l! b. G* J
the following sections the effects of jitter, present methods to reduce jitter, and application
6 Q4 {, K' c* I5 X/ aof the JAC will be discussed.+ R. m* \0 P) l) v
8 v7 b6 }0 F/ N$ C1 O9 E8 N7 e5 M& S
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