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AMD Geode LX 800@0.9W處理器
General Features
5 s, Q0 L* @. N, E■ Functional blocks include:/ d; @" i4 \6 U6 {8 Q, T
— CPU Core
: ]( |4 O# \. L8 _. A' I— GeodeLink™ Control Processor
0 A4 I( G9 k5 d9 f— GeodeLink Interface Units* q" w6 e* M4 y+ w0 L* }
— GeodeLink Memory Controller# I/ j$ j" p2 h! T& }
— Graphics Processor
1 [& v! {; T% _+ A— Display Controller
- o3 ^$ x6 [) ?9 S— Video Processor2 R4 T6 p2 `/ i [ t" n
– TFT Controller/Video Output Port
% W" O& U$ m2 t, j— Video Input Port
) p r" L$ S2 p$ A— GeodeLink PCI Bridge
; S# `& H* Q2 G+ v: e— Security Block4 |2 z+ k' c* }# d& W1 S3 K9 [
■ 0.13 micron process! ~( ^* ?! x2 Q% K# C9 C
■ Packaging:
; ]* o ]0 N) `, q9 C— 481-Terminal BGU (Ball Grid Array Cavity Up) with, j6 X) ^+ P/ Z4 O
internal heatspreader' U7 d. \. K6 M, y6 {4 _
■ Single packaging option supports all features
$ \) T$ `& a, `; v! tCPU Processor Features2 i8 j0 K8 P0 E
■ x86/x87-compatible CPU core) Q( Z* L8 X1 H, n) m5 G
■ Performance:
7 W2 f; I/ K# \- E' X+ F— Processor frequency: up to 500 MHz# R3 N* e( U0 I* O6 N
— Dhrystone 2.1 MIPs: 150 to 450
. j% t4 p* c% \— Fully pipelined FPU" K0 |% w: N# Y; h3 d
■ Split I/D cache/TLB (Translation Look-aside Buffer):
* o7 e1 k5 f. G. [* U— 64 KB I-cache/64 KB D-cache
2 S R* Z: h6 D5 J% y— 128 KB L2 cache configurable as I-cache, D-cache,
3 M' X$ \- A$ G1 n) ?" Q, dor both; e& E5 p% V) |6 ~7 x3 n7 Y: Y
■ Efficient prefetch and branch prediction7 L( k) I; q5 r9 t1 ^1 [7 @
■ Integrated FPU that supports the MMX® and& n! G0 C5 L5 ^7 m9 K
AMD 3DNow!™ instruction sets
7 n! }7 e3 K) ?■ Fully pipelined single precision FPU hardware with( X' ^7 `( K4 i! \# Q' ~- s3 X* ^, X
microcode support for higher precisions
, Y9 Z/ h9 W/ J$ i9 V3 A5 X& k/ c- H$ TGeodeLink™ Control Processor# B0 N7 ]% a% p& |' A* @( E/ a
■ JTAG interface:
0 b0 Z/ y( |, w' |( h— ATPG, Full Scan, BIST on all arrays$ K! @$ [. ?& q! F( z
— 1149.1 Boundary Scan compliant9 M6 y& H& p/ U1 y' z
■ ICE (in-circuit emulator) interface
& x- v0 i; k" Q9 _( i ^; e■ Reset and clock control
2 t! k7 y% P2 v" [! J■ Designed for improved software debug methods and4 C; P* Q$ h5 U* D
performance analysis0 y, _; [; G% O3 [ a
■ Power Management:
- i" S/ ^5 |2 ~. G, Q: T+ \% i— Total Dissipated Power (TDP) 3.8W, 1.6W typical @% R f7 E2 p E; h; U8 b
500 MHz max power
) {) P; L- X6 d# ]7 e! t— GeodeLink active hardware power management1 {5 T, X Z ~6 V8 ^& q$ z
— Hardware support for standard ACPI software power# ]! a7 }' T. p+ }
management
$ e5 y' _/ h- h— I/O companion SUSP/SUSPA power controls, ~, v# K9 E) K7 l+ r$ ^" W. P) t2 j
— Lower power I/O
2 D8 ]7 L( b! g0 c ^8 V— Wakeup on SMI/INTR3 l6 Y. o; s, E
■ Designed to work in conjunction with the: R) W3 ?* o8 t* d3 i( u* e, f6 m4 @" {
AMD Geode™ CS5536 companion device
! `* Y1 U" x! ?3 l) E) eGeodeLink™ Architecture: z5 n; j" T7 i1 W4 c8 ^
■ High bandwidth packetized uni-directional bus for
) [. Q; U4 @1 d# J( p/ w1 |; o0 Rinternal peripherals
; p+ Z0 @0 W& Y' z3 w■ Standardized protocol to allow variants of products to be
( R7 V) N: L4 I% r4 ]5 Gdeveloped by adding or removing modules
* e* I2 O9 N# K/ v7 ~/ z6 ]■ GeodeLink Control Processor (GLCP) for diagnostics4 d) ]8 ]% h$ I5 W3 S' v
and scan control
) b0 |+ Y" ?# g4 @■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
4 n& {/ p3 R- P3 ~3 x+ K4 kGeodeLink™ Memory Controller
+ O1 B8 |, K) ?/ z' V■ Integrated memory controller for low latency to CPU and( q$ T& C9 _; f6 G2 A
on-chip peripherals
2 B( Q' m5 Y9 }1 y: C■ 64-bit wide DDR SDRAM bus operating frequency:# k( r9 p* n, K) d/ E
— 200 MHz, 400 MT/S
5 P$ G4 }4 A5 P4 U: T■ Supports unbuffered DDR DIMMS using up to 1 GB
5 q* L# ?) a/ I- ^1 ^; VDRAM technology, z5 M6 Q$ W4 W
■ Supports up to 2 DIMMS (16 devices max)
! @( \3 a, i0 f2D Graphics Processor
8 j5 W1 S" v n: ]/ s: X2 t■ High performance 2D graphics controller7 N9 e" H) ~# `! W$ p2 ?3 d# o( h
■ Alpha BLT$ D3 s' ]) U9 d$ a
■ Microsoft® Windows® GDI GUI acceleration:# W8 S* {& }: L s. m4 }& m! |
— Hardware support for all Microsoft RDP codes3 w$ L/ o( h- h. m4 F' o+ a
■ Command buffer interface for asynchronous BLTs
z2 g" E! g) A- b+ o" p■ Second pattern channel support
5 k, Q4 R* N: b' r$ t: h■ Hardware screen rotation |
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