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AMD Geode LX 800@0.9W處理器
General Features8 [3 @* {7 I$ w% K0 [' p& S
■ Functional blocks include:
0 O. A4 a) S7 h3 ~! e" ~! J4 v" E— CPU Core' i5 m4 `1 k0 I. D: O
— GeodeLink™ Control Processor
8 @5 E5 t: g9 q4 a— GeodeLink Interface Units
9 `8 N- B- C3 @2 ]/ T" i- P— GeodeLink Memory Controller3 `3 |( E. v2 @% k, l( ^- l0 {
— Graphics Processor3 D- a: }4 I' B2 h
— Display Controller }2 A) y. s. u- @+ Y3 X' a. Z
— Video Processor$ v& p. b4 E5 |' g0 Y8 O Q+ m$ c
– TFT Controller/Video Output Port
. H' X1 E9 V- Q— Video Input Port
! y$ U9 {- J* E! c) T2 z— GeodeLink PCI Bridge g2 B8 k6 h2 n5 x; U2 X
— Security Block
3 i# X( P0 y, i2 Q4 ]1 p4 t■ 0.13 micron process
* O' ]2 t7 I6 x8 e4 U■ Packaging:. [/ L1 ~% l, \( A) ^
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
8 ?6 \0 y4 y7 ]' z+ N* sinternal heatspreader, [* ` K, l$ \& ~# |2 U5 q9 p
■ Single packaging option supports all features
: F% ~7 V5 o2 m* t# rCPU Processor Features
0 P! D) `) @& v& i■ x86/x87-compatible CPU core5 T. j8 T& r( T* {
■ Performance:
# s! g7 Y7 ^7 R8 B/ f! j7 \— Processor frequency: up to 500 MHz
1 Q, x, D+ e* L— Dhrystone 2.1 MIPs: 150 to 450/ [, y6 b I5 Q) H& B
— Fully pipelined FPU
. Q2 W# [ R' b3 n■ Split I/D cache/TLB (Translation Look-aside Buffer):
4 a% H7 a- `" Q' A* n6 `3 X— 64 KB I-cache/64 KB D-cache
2 T7 z8 I2 z8 l1 ?4 G+ H— 128 KB L2 cache configurable as I-cache, D-cache,+ _6 t' v( s8 a* c. a- x$ O2 s* z
or both
2 p- e8 C% u# l p■ Efficient prefetch and branch prediction" C& v G' C0 L S/ r$ S& `
■ Integrated FPU that supports the MMX® and
. k3 c% {5 d+ }AMD 3DNow!™ instruction sets
+ k! A8 @4 L8 \* f" T+ }■ Fully pipelined single precision FPU hardware with
3 g$ c, |9 e/ omicrocode support for higher precisions1 f( E5 B# M- L4 N1 c/ t+ Y
GeodeLink™ Control Processor- m9 B; K( q4 G) f2 z0 l; }/ Y
■ JTAG interface:( w1 E' N& w! z# Z- j0 V" G
— ATPG, Full Scan, BIST on all arrays
5 [8 s2 g( V2 ?) R( {— 1149.1 Boundary Scan compliant
' x" V/ u/ A. j. g1 n' a5 ?8 S■ ICE (in-circuit emulator) interface
0 S9 @& B9 s a+ _$ t7 q■ Reset and clock control- |5 M* \" [+ {# Y& Q; i7 x
■ Designed for improved software debug methods and
2 k; n: A: l0 s4 W( q8 B. }5 Aperformance analysis
% ?8 x) ]" ]$ K* D" v% V/ _■ Power Management:! d1 j/ `* F, R! e
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @: U5 k) D' U! p9 s
500 MHz max power4 \$ ~) Q/ O" O/ y7 D! ~
— GeodeLink active hardware power management) p; o1 ^) v1 W; C
— Hardware support for standard ACPI software power
' A$ T4 b6 F* b+ ]5 }1 umanagement. u+ W0 j6 Y$ f2 r" b' J; M
— I/O companion SUSP/SUSPA power controls
, k. e8 ]- ]8 ?$ Z8 J) z— Lower power I/O
* z" e6 o5 n2 `: g+ C: U— Wakeup on SMI/INTR
* x9 S) X5 `* e■ Designed to work in conjunction with the: B# s$ v& Q& \" {, s$ Q* v
AMD Geode™ CS5536 companion device
" B d* f* I, J6 ?2 ?5 S5 M2 PGeodeLink™ Architecture+ `( `! f2 Z @2 s, F3 q
■ High bandwidth packetized uni-directional bus for
! N" P# D% f7 Z; D. c; Binternal peripherals
# L) O3 M4 ~2 G# B■ Standardized protocol to allow variants of products to be
1 r$ K6 }8 a+ Odeveloped by adding or removing modules" \% [/ p" ^# o2 X
■ GeodeLink Control Processor (GLCP) for diagnostics
: p- |: d- J, Gand scan control3 ^2 k' E$ G5 P( o) T1 u
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
! Y) c9 J# Q. z% n3 {% X/ NGeodeLink™ Memory Controller
0 a+ ?' A" n: J4 m■ Integrated memory controller for low latency to CPU and
, r# y! c; e. N* {+ X B9 D% Pon-chip peripherals, \- d* o8 h/ P h) w5 s
■ 64-bit wide DDR SDRAM bus operating frequency:; i3 c9 h8 c4 ]
— 200 MHz, 400 MT/S+ b9 ~/ R" s, o% K4 J- F
■ Supports unbuffered DDR DIMMS using up to 1 GB6 u/ b6 u' t. Z3 T. c
DRAM technology1 D6 |- {" ^+ `
■ Supports up to 2 DIMMS (16 devices max)
: _# r9 M: @: p! K, I- X i2D Graphics Processor9 w1 W* c/ f s( Z' r$ u
■ High performance 2D graphics controller. R/ e3 d3 h: @6 s2 u: }0 u9 |
■ Alpha BLT( C# `: C! ~2 j r
■ Microsoft® Windows® GDI GUI acceleration:) h. H: P$ ~$ ^9 ?# L
— Hardware support for all Microsoft RDP codes
4 `( I D- |5 w# L: t& x■ Command buffer interface for asynchronous BLTs9 F8 H: E' k& f' a8 m1 B
■ Second pattern channel support$ m- \3 L9 n; I
■ Hardware screen rotation |
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