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發表於 2008-11-26 21:59:05
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IV. CONCLUSION4 }- U. y9 j+ a" r! n" t N- @
The designs with 3-stage-inverter and 1-stage-inverter# n( T- C2 X% v5 W( M$ l% h; P
controlling circuits have been studied to verify the optimal/ a& |* {% B4 L L1 |, V! S: O
design schemes in NMOS-based power-rail ESD clamp* n8 h/ ]/ H9 R1 p9 z! a
circuits. In addition, two ESD clamp NMOS transistors,
Q1 z9 B% M4 Y$ P; d2 f! Ihaving snapback and no snapback operations, also were codesigned
4 l8 B, g2 p; c7 G; awith different controlling circuits to realize the6 D' Y; [, A# z2 F7 i' J
impact on their required performance. According to the
- y* W: h% T1 n; m( }. Sexperiments and analyses, the 3-stage inverters can slightly
% U2 q' r% [/ U( ^, }. i. [1 zincrease the ESD robustness, but they also can dramatically. k4 K5 K) J* t y. c0 I/ w: O! s- s
sacrifice the mis-trigger and latch-on immunity. The 1-stage- E& @. U( T$ n0 w. U
inverter should be an appropriate and reliable candidate for the
4 y0 C3 @: r$ W8 F8 Y& Q/ Upower-rail ESD clamp circuits. |
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