Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

& K" I8 `9 G0 g! UKaran Bhatia and Elyse Rosenbaum
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
1 v1 C. m) I# F1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu

9 e& N5 {. o: @7 d# O+ c2 L% M4 qAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
. }3 y1 D9 c! C+ a# F5 R* _* O, s' xcapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
: u; \; s2 L7 E/ R1 ~* X2 M9 T- kperformance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
I/Os [1]. Layout-optimized ESD diodes provide a
' N) b3 k0 j. f) x6 P  e4 N+ N$ fhigh protection level per unit capacitance (C),
; e+ e0 V7 L1 l4 [! C3 aminimizing the performance degradation they induce
5 ^& X. T5 w8 c  eon high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
" m0 |3 X6 H' s) V
讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
, L7 Z, u# y, h+ r現在急需esd的防護方式