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CMOS Transistor Layout
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Copyright © 2005( j8 w/ T8 t& F% B' v) S* g
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Table of Contents
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4 V9 j/ o2 d4 @; e# @# IPreface
" U, E$ j- m1 p9 }1. Introduction .................................................................. 1
7 L& M0 u {! D3 o2. MOS Transistors ........................................................... 2
: e/ \6 k9 {' r6 j6 K* r3. Fabrication of MOS Transistor ..................................... 56 s2 `! w+ d. w6 a3 t
4. Layout a Single Transistor .......................................... 11
; X7 v; R+ x/ H+ b& s* F! yFirst Stroke The basic transistor layout ..................... 12
# F* `+ D9 @8 d, a2 } a# o1 VSecond Stroke Compact the transistor layout ................ 13
" Y8 D' P8 Z9 x" _/ n/ u& gThird Stroke Speed up the transistor ........................... 173 p+ K9 y$ t2 I2 v
Fourth Stroke Clean up the substrate Disturbances ...... 20
( l% P3 w: w1 F2 EFifth Stroke Balancing area, speed and noise ............ 26
. Z+ }: _+ ]4 {6 r# Y; l8 BSixth Stroke Relief the stress ...................................... 29
5 F: G7 u" m4 fSeventh Stroke Protect the gate ...................................... 30, ?3 C: i. S4 j/ O: f% k4 F+ ^
Eighth Stroke Improve yield ..........................................32* x1 }4 c, v0 q6 w
5. Layout Several Transistors ......................................... 34
6 P. P5 [/ l0 l8 c7 R8 xEighth Stroke Improve yield...........................................35
7 ~) ?( d/ }& p' M* }2 K1 z: ~& BRe-visit, Q- Y. ~, q9 g# {- o
Ninth Stroke Close proximity .......................................36# a/ j* f/ J) ~0 S/ I
Tenth Stroke Interdigitated layout ............................... 362 U5 x9 n0 Y1 m0 w: u6 u
Eleventh Stroke Dummy transistor ................................... 41
& }9 o V" J) ^4 T* F9 o& ITwelfth Stroke Two-dimension interdigitated layout ..... 430 A! G5 T" j0 Y+ z
Thirteenth Stroke Guard ring for the matched transistors ... 45
6 U) b! U- {2 VFourteenth Stroke Keep NMOS away from N-well ............ 45. E o% l5 W! U9 Z
Fifteenth Stroke Orientate the transistor ........................... 462 n4 H& ^/ ^3 T) A% o
Sixteenth Stroke Match the interconnects ......................... 47+ l% }0 y0 o! T" u$ V& U. n: b
Seventeenth Stroke The unmatchable .................................... 504 E' _3 O* I9 k
6. Verifying the Transistor Layout ................................. 52. C) ]7 X# v" r! K
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[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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