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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
; }4 I4 H% G8 |+ ?5 W3 ?1 }" TAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
2 G1 j. z* h+ }% A6 C. ?2 J, Pon par with commercially available PLLs, while being relatively simple to design and use as
3 H- n4 s2 e% @5 i+ K1 l' @5 P6 Qan on-chip solution. The main difference between the JAC and PLLs is that the JAC does$ C* V5 E7 l% H2 A( `9 I
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In8 d' P% K7 I: X! f# y" w
the following sections the effects of jitter, present methods to reduce jitter, and application% I/ r9 x& d* T- x0 t0 p1 q
of the JAC will be discussed.( S3 {' Z$ |9 [
5 a; ~$ g0 _4 A' k3 k" I
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