|
This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter. t: p. Q$ _" J. S8 [
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
. M+ u) P4 W* T0 won par with commercially available PLLs, while being relatively simple to design and use as+ g7 [& l. x. F$ U4 [
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does5 V# m) v7 O. F! F/ N) z
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
) Q5 d9 \0 L4 z, t2 j% u2 hthe following sections the effects of jitter, present methods to reduce jitter, and application2 q6 m2 N3 O( I
of the JAC will be discussed.
1 r/ O6 L1 O" G
7 I0 K+ @3 I3 I( | |
本帖子中包含更多資源
您需要 登錄 才可以下載或查看,沒有帳號?申請會員
x
|