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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
. M u8 B. `: K0 B! z4 {( d, HAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
6 ?' x5 a2 a: p, Y3 }! d5 Lon par with commercially available PLLs, while being relatively simple to design and use as+ H3 T* c% {, I9 V2 p, X
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does/ [: K0 L/ r2 k' k9 ^
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
( ?0 b8 t, Q2 i. S* \( nthe following sections the effects of jitter, present methods to reduce jitter, and application
9 Q3 T" P* J& R$ Nof the JAC will be discussed.# R0 f% `- U3 F$ W0 D: M
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