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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter6 ?0 P0 n- }- r5 P% d
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance: g9 D* ?; V3 I. d
on par with commercially available PLLs, while being relatively simple to design and use as& Z! L& I/ ?( ?6 n* x! y, C) e' u: c
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does+ x) y% t6 Z5 _% e1 ^) n9 Q8 Y
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
: T' e# p9 I/ kthe following sections the effects of jitter, present methods to reduce jitter, and application
* i! z) p7 t8 J. M- Q( qof the JAC will be discussed.% T$ H9 `6 z! M; @- i; r3 b* I& d, i ]
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