大家好，我是新成員，問一個小問題

kyopc

首先，感謝各位撥冗來看我這帖子
這個問題算不上是設計，是一個小小的問題
我現在有一個CPU的source code,
memory的部份是有一個interface來接收FPGA晶片外部的SRAM資料
& G2 X. o+ j6 U$ [, Q7 [- M$ Zmemory資料寬度32bit的

0 u; g% l0 \+ a3 O+ I( Q要把他download到我的板子上
但是我的板子上的SRAM只有16bit
' f3 ~) o9 a4 |7 ]" D請問我要怎麼改寫裡面的VHDL code來符合

可能對板上的高手來說，這是基本問題
但是我本身不是VLSI設計背景的人
老闆硬要我搞出來 >_<
5 i2 K$ l! J0 x* q; b
( g% m' E) s6 u3 \& n% j希望大家不吝給我一點提示,謝謝大家

tommywgt

就算是32BITS CPU也允許16BITS的存取才對, 在這情況下, 什麼都不用修改的, 只需要修改軟體的程式

- j$ b; Y* R* m6 G9 F如果一定要做到軟體都不用改的話, 影響的範圍比較大, 你可能需要:
% t" o! e9 ~' \6 Y1) SRAM工作於CPU的兩倍頻率
) c8 M! x" Y+ |$ w* |" w2) 利用類似BE信號 (BYTE ENABLE)來控制SRAM的存取
) |5 k9 }' [5 D* ?: o3) 如果SRAM速度跟不上CPU, 而且又不想降頻的話, CPU要能支援類似BUSY的控制信號
4 Y9 n% A5 H( A2 b, a1 c4 o) b! [差不多如此吧, 還有其他我漏掉的嗎???

jason_lin

沒錯,就版主的方式,不然就設計一個FIFO SRAM Controler,丟到fifo裡,讓他自己丟到sram,
, O6 l" Y5 v1 k% ~0 F# k如果完全不會寫hdl,那你去網路上收尋,應該有人寫好的吧!
不然Xilinx有提供memory的參考設計,有含HDL code,如下列網址:
- C. E$ \1 D- W& ]0 [. N# Ahttp://www.xilinx.com/products/design_resources/mem_corner/
你找找,Xilinx的參考設計編號都是XAPP***.pdf,裡面有一個Design file的網址,就是下載soure code的地方^__^
: }2 k0 H2 u/ E  T2 L# ~) L

kyopc

感謝兩位前輩的指導
5 a0 l  \4 h: p7 D6 D* P7 A由於工作需求，我的程式是沒辦法改的
換句話說，我必需修改我的硬體

我會先試試看jason大大的方法，結果再回報給大家
2 {$ T& A  B& N" k9 v4 I) R9 L% e7 @6 t提供經驗給大家
! v/ H  V. }- T$ q1 e/ u8 u- a謝謝

tommywgt

Xilinx的XAPP好多, jason_lin有意願整理歸類一下, 發個文跟大伙介紹一下嗎?
就以Xilinx的Vertical Segment分類來整理如何?
另外並不是所有的XAPP都有source code的, 可能也要說明一下, 大伙才能更清楚.

1 E2 i! s9 U, p5 x. ]先謝囉!

jason_lin

我整理了一些而已ㄝ,如下:
FPGA
/ t: I2 G( e0 L$ KXAPP058        Xilinx In-System Programming Using an Embedded Microcontroller&nbsp;
+ o% W. P& R7 C' jXAPP195        Implementing Barrel Shifters Using Multipliers&nbsp;
XAPP211        PN Generators Using the SRL Macro&nbsp;
( K' ^; [+ t: }$ E; z1 n9 hXAPP217        Gold Code Generators in Virtex Devices&nbsp;
. S, P( {( r" U% W( V7 o- xXAPP220        LFSRs as Functional Blocks in Wireless Applications&nbsp;
' d5 n9 m2 \2 a$ @XAPP224        Data Recovery&nbsp;
4 i0 T0 h  E) V, s) oXAPP228        Quad-Port Memories in Virtex Devices &nbsp;
XAPP229        Wider Block Memories&nbsp;
XAPP250        Clock and Data Recovery With Coded Data Streams&nbsp;
. r* q0 T$ |! vXAPP258        FIFOs Using Virtex-II Block RAM&nbsp;
XAPP260        Using Virtex-II Block RAM for High Performance Read/Write CAMs&nbsp;
XAPP261        Data-Width Conversion FIFOs Using the Virtex-II Block RAM Memory&nbsp;
" o& _! \. E; p' S. Y  pXAPP267        Parity Generation and Validation for the Virtex-II Series&nbsp;
XAPP268        Active Phase Alignment&nbsp;
XAPP284        Matrix Math, Graphics, and Video&nbsp;
XAPP291        Self-Addressing FIFO&nbsp;
$ v8 Y$ J6 W  \! {0 cXAPP441        Remote FPGA Reconfiguration Using MicroBlaze or PowerPC&nbsp;
XAPP445        Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories&nbsp;
XAPP454        DDR2 SDRAM Memory Interface for Spartan-3 FPGAs&nbsp;
XAPP462        Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs&nbsp;
. B/ h+ D! Z( \7 f" y$ zXAPP463        Using Block RAM in Spartan-3 Generation FPGAs&nbsp;
8 Q$ R; d8 ^' @) bXAPP464        Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs&nbsp;
5 H5 V0 o9 j* o: r) l( n; xXAPP465        Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs&nbsp;
: ]! q( S$ G  w/ A  \0 V/ hXAPP466        Using Dedicated Multiplexers in Spartan-3 Generation FPGAs&nbsp;
XAPP467        Using Embedded Multipliers in Spartan-3 FPGAs&nbsp;
4 Y. P* C3 Y% ^XAPP473        Using the ISE Design Tools for Spartan-3 FPGAs&nbsp;
XAPP474        Using IP Cores in Spartan-3 Generation FPGAs&nbsp;
) T6 H) F! N8 T5 V1 p2 uXAPP475        Using IBIS Models for Spartan-3 FPGAs&nbsp;
XAPP476        Using BSDL Files for Spartan-3 Generation FPGAs&nbsp;
! q7 @1 ?' \# t9 Q+ l9 z* MXAPP477        Embedded Processing and Control Solutions for Spartan-3 Devices&nbsp;
  F6 N0 I( B/ v: |XAPP482        MicroBlaze Platform Flash/PROM Boot Loader and User Data Storage&nbsp;
! K+ _: q" V* v- ~2 vXAPP483        Multiple-Boot with Platform Flash PROMs &nbsp;
# ?, K" p0 o$ y. i8 T7 F) k7 ^XAPP485        1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps&nbsp;
XAPP489        Four- and Six-Layer, High-Speed PCB Design for the Spartan-3E FT256 BGA Package&nbsp;
7 X% Q* `7 r0 z: v7 zXAPP491        Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs&nbsp;
XAPP500        J Drive: In-System Programming of IEEE Standard 1532 Devices&nbsp;
XAPP502        Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode&nbsp;
8 E$ l, U. q6 n2 L9 Z6 a* m, |XAPP514        Audio/Video Connectivity Solutions for the Broadcast Industry
( N2 k& C  [, k5 EXAPP529        Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link(FSL)&nbsp;
+ G; Y: Y2 P  D. C) tXAPP535        High Performance Multi-Port Memory Controller
$ ]2 H' n1 E8 N- C) P2 k8 h1 @& ZXAPP536        Gigabit System Reference Design (XAPP536)
+ `9 |& R/ z! x0 j9 u  GXAPP562        Configurable LocalLink CRC Reference Design&nbsp;
XAPP569        Digital Up and Down Converters for the CDMA2000 and UMTS Base Stations&nbsp;
XAPP622        644-MHz SDR LVDS Transmitter/Receiver&nbsp;
XAPP623        Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors&nbsp;
0 ^  I" `* f' w* v$ uXAPP634        Analog Devices TigerSHARC Link&nbsp;
/ l  Y* |6 j; d) r  [. ?XAPP636        Optimal Pipelining of the I/O Ports of the Virtex-II Multiplier&nbsp;
XAPP689        Managing Ground Bounce in Large FPGAs&nbsp;
4 n+ Z5 n6 \- K% Y! P3 ~XAPP690        Using Block SelectRAM Memories as Serializers or Deserializers&nbsp;
: A2 x! P/ A5 K; t* j1 z" C- MXAPP693        A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs&nbsp;
+ m+ J6 Q* Q- O, z4 P! QXAPP694        Reading User Data from Configuration PROMs&nbsp;
, N0 x2 ~, V+ B" u% g- @XAPP753        Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF&nbsp;
XAPP774        Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs&nbsp;
& ^$ P) \5 b7 t* Q4 N; o5 ^9 h- XXAPP780        FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs&nbsp;
XAPP806        Determining the Optimal DCM Phase Shift for the DDR Feedback Clock&nbsp;
; O3 ], h/ w4 h: N4 R) ?XAPP909        Reference System: MCH OPB SDRAM with OPB Central DMA&nbsp;
( I6 k6 u4 |& s2 N9 c8 mXAPP923        Reference Design: MCH OPB EMC with OPB Central DMA&nbsp;
9 d2 J! p$ z: n8 e5 b" zXAPP930        Color-Space Converter: RGB to YCrCb&nbsp;
0 |( s7 V: F, ]5 [' x1 mXAPP931        Color-Space Converter: YCrCb to RGB&nbsp;
" S5 |" V; A# dXAPP932        Chroma Resampler&nbsp;
XAPP933        Two-Dimensional Linear Filtering&nbsp;
% e5 E: D& M1 @8 u  WXAPP936        Continuously Variable Fractional Rate Decimator&nbsp;
XAPP948        Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurement Using System Generator&nbsp;
XAPP253        Synthesizable 400 Mb/s DDR SDRAM Controller

tommywgt

能有系統的整理嗎?
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" f. g' [3 S: G1 F: M, y8 x造福大家靠你囉...