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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
3 R! Z1 j6 L- g# `( r* z% ^& p& v$ C5 A
請教業界各位先進# u6 {) T! r& g* ^) P  C/ S
目前的chip開發,需要多少投資?
! Y& H* o- C+ {4 g首先是假設 Febless design house.1 h2 D& Q! m9 v4 G& X( B
自家由algorithm 到 RTL simulation 完成# M' P. @4 n5 V, h7 _' B
後端包給 backend service 公司 (layout, mask, Fab, assembly..)3 A. e4 J: }6 V9 x
以 ARM9 or ARM11, AMBA2.0 為platform
* a# I. Z* o9 \' d+ o" ?4 }. L7 G那麼3 {5 S( h" }8 g* Q
  (1)90奈米, NRE大概多少?' V0 E5 m, c4 Z
  (2)65奈米, NRE大概多少?
; C! u! \) u2 Z* A  (3)或是您知道其他製程, NRE大約多少...
  i/ T2 P4 E* G# X+ k
$ v+ M8 P, a* H9 R" ?謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
' c+ H& h: ]' s& j, r+ q! q* sHow many mask layers it will be?
) \8 C- {0 u% J; H- p; nBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?& p: L7 T' n) z# _
How many chips you need? A full set mask or MPW?1 j# I7 z# J( Z1 S4 A
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,( E1 D0 {% M3 y& G8 ]$ Y0 S

; X+ l. x# h% {: ]I just estimate the investiment of a ASIC team.
4 f, |: B: l' f: Fnot servey for a project.' v3 v) r$ h( ?' T2 M
So, I just want to know the range of NRE./ V, _% d( N" |8 a

6 Q5 n, C; E( ~1 d' I! O* rFor example, It will be 8 V( L, p! h/ G( X0 r' t
(1) 5,000,000 NT$ ?! h/ f1 Y0 |9 L4 }
(2) 8,000,000 NT$ ?
" ^: w$ A5 j$ g  b% W2 v: g(3)10,000,000 NT$ ?
; X, ~% T# [' T) i7 _(4)12,000,000 NT$ ?
* t  z! K5 O9 W6 e0 r( Y5 U(5)15,000,000 NT$ ?
) W3 B7 Q4 L4 w0 k8 a* X: ?1 a( o4 L) P9 v/ a; d4 x' u
Sure, I understand following things:
) Z. g# I; ?) P  {5 u, F* X - full set mask cost more
7 T& c) E4 y( E% D - PLL/LVDS... analog IP are extra cost  O- P1 F( ]* n: u" K
- pin-count and area also influence cost' `5 D9 D" @* L9 `. v
- different package also cost different
1 n" c9 m0 V' j! S% l, f% N! ]# g& D6 e: m3 L1 G! i' k
Therefore, if really need information for estimate,
; T  X2 p/ i6 Kjust for example.
8 F0 ^! y/ w* x) \- f- T9 p& PLet's assume a SoC for FullHD TV application
/ _; T$ Z' O* G1 a5 z+ Mit will include
$ _9 E' {- b. d- O4 ~, d) @  - ARM AMBA
- b  R, q; ]2 |% d0 D  - DDR2 I/F
5 B; B$ Q: Y- P  C4 c( E  r  - GPIO, IIC,...2 C% B. o& K$ Q' b+ s
  - LVDS out (dual link)
1 k  r" u4 [* W3 D. A$ y' x( E; O- G  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
+ ?3 K) L3 k1 m4 S  A: I  - 12bit ADC, 10bot ADC x2/ H2 M% w, D/ z7 i$ z
  - PLL/DLL
7 E6 |# L& G" w: J& @- D  - 256 pins 以上
- @, j; Z$ @9 F) Q4 F; y
4 k7 |( U* S+ J3 s0 @' v, T! Z9 lThan,... any idea about NRE fee?
* }3 O, \1 E+ [- E4 Gagain, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
/ }7 y( y  ~9 w  H! p: wbasically 65nm-->USD$1M above and 90nm-->700K above* |8 ~8 \; f& Z
and base on different foundry has difference price!
# q* f9 x1 {4 B6 u* O+ ~5 d% xthis price did not include any specific IP like TV encoder, decoder, vedio codec....  G3 R) p5 v( L! C  B% @8 G/ D
and did not include the ARM licensee...
: A/ p. H0 W! H4 X, sactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)* ]. V4 ^* a- c, v/ U8 H
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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