靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

ritafung

thanks wesleysungisme for your answer.
: G& u* y' S$ |2 Y4 Y' `as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
6 e% }: N' S$ p& w8 m有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

wesleysungisme

For ESD test (HBM)
The following are the test combination:
1. Power to Power
) _7 H" n7 A& k4 m& ~/ }! ]" B2. Power to Ground
3. IO to Power
4 C7 G+ I! a/ [4 b+ `% e4. Io to Ground
5. IO to IO
1 u; A1 x8 ^% i: c. z' S) ]1 A(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)
: y1 B% o- T0 p! d; V# o" k
the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
# o, {& k! I/ O) k7 I5 K- X( aFor example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
3 ?; L' w: m0 @8 C4 ZSo for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

$ X- I. M% t; ]2 ^. uFor your reference.

ritafung

my company is pursuading to MIL-Std ...
actually any company need MIL-Std? Our application is not for military purpose....

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
# D( I1 m  G+ T. g8 y! d我的建議是去閎康，會比較適合。
! y5 w* E0 O' H7 X因為我本身工作性質也是有接觸到ESD測試
2 i: d8 n2 O7 |9 E$ X2 u測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
在Zap的次數明顯比軍歸來的少了。
9 g2 H' r4 Y( t2 P* Y

cuban487

很多實驗室好像都有,但都在台北.
儀特好像就有可以去查ㄧ下

m851055

竹科閎康科技有此業務
/ [# Z6 B1 L1 r5 {電話在網頁就查的到了.......................