Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

, z' m. y7 f& Z9 W+ b* q2 LAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
+ l* L' w0 @$ Udesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
1 H. y1 c8 `+ R' W1 @! E4 `5 I
: Z) T* u" x0 c+ T8 x$ P注意：内容有一定深度，初学者可能看起来有些困难。

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semico_ljj

IV. CONCLUSION
* g- o4 V' z/ K9 ~5 j: NThe designs with 3-stage-inverter and 1-stage-inverter
0 x- o  ?% r! j3 _1 ^# F: qcontrolling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
impact on their required performance. According to the
7 I( G9 E4 T" U& K3 V9 O/ Vexperiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
8 @! ^1 ^' w$ asacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
5 E( m7 u- [" I2 t6 ]power-rail ESD clamp circuits.

aicder

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kevin5461

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layes2

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jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！