Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
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# E4 L; u. N" E: \5 [; JWen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

6 N6 N/ _5 w/ |* W" C, @Abstract—The n-channel lateral double-diffused metal–oxide–
8 ]  G" T2 o+ V8 l8 C/ ^/ ?  }semiconductor (nLDMOS) devices in high-voltage (HV) technologies
are known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
8 H3 k! d& |1 lmethod combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
9 x% f% s, u5 @$ o0 {in this work. The proposed layout and circuit co-design method
on HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
& ], {& O% M5 O2 \process without using additional process modification. Experimental
* x; n: D' H# w8 D: A9 qresults through transmission line pulse measurement
* P* h( Z8 W" x, M( L* M& D% _/ ^and failure analyses have shown that the proposed body current
0 p$ t7 ]. Y, j! G; winjection technique can significantly improve the ESD robustness
3 I$ L8 g1 d, m7 vof HV nLDMOS.
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6 i6 \, x  N6 Z4 y! s6 P( K- zIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
, j+ X4 V4 V' y6 T$ J% q4 scurrent injection, electrostatic discharge (ESD), lateral double-diffused
- v) C- {3 e+ l6 ametal–oxide–semiconductor (LDMOS).

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