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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
& Y( r* {2 `* i" e& q2 {: v% CAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance, w. J3 B1 B6 Q- X9 h( e
on par with commercially available PLLs, while being relatively simple to design and use as3 [% ^& N: H# Y& |
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
" \, y$ E* ~; o W1 H2 Fnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In M( @$ e7 ?3 T8 u' R
the following sections the effects of jitter, present methods to reduce jitter, and application
3 j3 d8 h: V. D. b) j7 w1 K" Mof the JAC will be discussed.
( `. T" S: b" y& D) d" z1 ]) ~# d4 z* w: b
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