hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

1 R- R, W  b& W) e; w/ @: n. a要怎麼定義用
plot LX??
. z& q9 V# Z, _, c" ~
請各位幫忙一下

小朱仔

直接下.op及.probe
' U. l6 M- F& `5 E( t找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


# ?5 z* `% h. X8 ]For your reference.

0918429587

CAB_BS    LX28
! J" }: |. ~6 y+ ^/ c3 G+ \) HCAB_BD   LX29

其他我找不到
# q; V" m% t" }Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO
. G8 r$ H+ K5 P9 N0 ]: _' h8 Q; w4 B
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
; O# e4 F7 g% zAn example for your reference...

----------------------------------------------------------------
$ {$ `" z' [- k# [% q  I***** Gate Capacitance Plots *****
$ N6 `5 `3 R. \; `7 u$ T.lib 'your_component_model' lib_corner
/ K3 y# L) \- o  D.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
) E( F, t  W/ ?+ r" evg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
4 e# U5 M5 }* l8 b3 P6 z& x1 O( o5 N.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
1 Q% M; J2 H# H6 Q: i% ~+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
5 I/ S6 _! {! m; V) \+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
Six capacitance are reported in the operating point printout
    cd_total = dQD/dVD
    cg_total = dQG/dVG
9 z0 ]( v  x: Z# j    cs_total = dQS/dVS
6 j$ ]- v. S- F0 ~: M    cb_total = dQB/dVB
    cgs = -dQG/dVS
( W3 e: f  l2 R! g3 m/ Z5 i: g    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
" D: R" g" O# U. L) Moverlap capacitance, and drain-bulk and source-bulk diode capacitance.
2 Y% }2 u, J; P& j4 q5 `7 L" e
0 p3 v; Q9 F2 u3 H) ?& q" `& ACGG = dQg/dVG
CGD = -dQg/dVD
" ?# ^, r8 S6 M% g" fCDG = -dQD/dVG
3 A) |; T, z6 J6 e" K0 B5 k1 M
The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
- M$ D" |8 E+ l# eLX20(m) = dQG/dVSB = CGSBO
/ S$ E, q) b$ t% [$ S! p- ?
. V+ w+ j" L7 U) T# O9 g1 m) aLX21(m) = dQB/dVGB = CGGBO
1 e4 {3 c+ x0 j( M, F: r' I1 QLX22(m) = dQB/dVDB = CGGBO
5 o& t2 m- Y- d; o8 }LX23(m) = dQB/dVSB = CGGBO
7 A; Q$ W) F$ |9 g! p
LX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

8 i4 {( V+ f  x1 [6 t. rThe equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^