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實驗平台~
/ C8 u/ M9 K- \「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA1 v5 ^4 S2 V3 I, i$ K3 k
在建構的過程中(僅放入cpu跟memory ip)
" K2 c( B6 e+ Z% p. S% | tno reset vector has been specified for this CPU0 K5 ]# E. v5 m6 Q
no exception vector has been specified for this CPU
7 A, V) U, ^% o這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎
9 Z. q& }& V+ B& N2 C% L試過- l( w2 R8 r* R5 w' o$ Q
on chip memory" D( h; e" H) D' n
sdram
& t& Z+ R) X, f9 V$ Y" }$ d5 b x用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)/ Q. |+ V2 @# i/ Y n+ C3 z0 ~+ D- ^
no reset vector has been specified for this CPU) n8 l' ~7 q( F% t
no exception vector has been specified for this CPU
" {: d. A4 P5 O; R" y- `總是會有一個沒辦法去除(先選的訊息會被消除)
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有人有在玩10.1版嗎?請多多幫忙~~
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3 i* O4 G0 _6 |) v' ]( L4 R目前打算~改用10.0sp1跟9.1sp2試試看
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THX~ |
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