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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
( j/ D z8 c8 N5 MAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
; ?4 d% h; Q1 C$ F8 S/ f/ L3 Non par with commercially available PLLs, while being relatively simple to design and use as
6 z3 N$ {7 _, ~ O$ S& ]4 u+ P! p% |an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
\: k* b' z& P) f& fnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In6 P. |0 Q8 M* l% C' C( t9 [
the following sections the effects of jitter, present methods to reduce jitter, and application$ ?- N. z/ z* G" U1 j/ f
of the JAC will be discussed.
5 e, d& w& K9 p9 D0 f3 r& J- j$ y' h! [. ]
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