|
各位:现做mixed-signal仿真,使用的工具为spectreverilog,随便做一一个电路,现在报以下错误,不知道是怎么回事,望各位指点:
0 d x9 R4 z& d' r0 ~0 W# v该错误是在做以下操作时显示:Mixed-signal/Display Partition/All Active3 r- O( j9 f" b' ~ n
error: failed to partition the design.
& z" ^/ h8 A# g3 d2 t5 W0 l8 b ......unsuccessful.7 Q- j; V @) l, r% g* ^
error: cannot create and partition the design.5 U$ j2 T0 `. n! ^& _" M& f- X- c
error: must fix design errors before netlisting.5 S9 a; j! w/ [' o6 B! Z: ?
4 K7 b/ i& L, @( k6 |3 e) I5 }PS:在做混合信号仿真时,需要注意些什么?有什么比较实用的资料可以参考,多谢! |
|