hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

2 [3 i: x" S% z要怎麼定義用
plot LX??
. y  \  m3 [0 D
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
7 i0 `3 R( s7 T+ M! C6 |! R

For your reference.

0918429587

CAB_BS    LX28
$ U( P! m+ |% |1 N3 b$ ]$ ^  O4 gCAB_BD   LX29
4 w1 }" A+ \# L1 J5 E
: g5 W% r3 B2 T0 H5 G# ^6 T其他我找不到
" N* X0 K2 X& d5 @: T- C& n7 p5 o+ {Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
( f$ l* d, \/ K; D9 z這是 CGDBO  CGSBO CBGBO

: a# G7 @1 K! l8 t, P3 @* i/ j不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...

, `4 D2 c5 m. ~5 d- |6 y----------------------------------------------------------------
***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
  @9 q+ N/ S8 W+ @0 _; _7 em1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
+ J7 M! Q+ r! S( [vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
) ]* t! c& Y9 W.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
4 R: M3 P1 P1 u. A9 I2 _+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
( w' h( {2 l/ l# ~6 Y1 m! RSix capacitance are reported in the operating point printout
    cd_total = dQD/dVD
    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
$ S4 B5 u) ~! `3 d. L4 `    cgs = -dQG/dVS
5 d* C$ h% L' Q9 B+ S' M! L) ~* M    cgd = -dQG/dVD
* D& ?; }& ]. K# N8 k% F2 yThere capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.

CGG = dQg/dVG
6 I+ v# R' _8 P4 g7 `6 X$ FCGD = -dQg/dVD
CDG = -dQD/dVG
, f$ M: B8 K  D- r7 i+ i: r! G
The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.

( J0 {  h: \! N# U3 CLX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
" f/ T$ N' g3 {+ [1 I0 cLX20(m) = dQG/dVSB = CGSBO
8 Z+ _. z  N5 h% W  u( P! U0 e8 Y; v
9 U) p& W$ O7 W2 |3 ZLX21(m) = dQB/dVGB = CGGBO
% L! d8 U- O' M  a# {LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO
" K6 X3 Z  t, l+ n
LX32(m) = dQD/dVG = CDGBO
  [* T, s% C: `LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
1 H: @1 x' h  h3 l: r0 F! E
The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^