ARM的領導地位正受到Tensilica的強烈衝擊

jiming

ARM的领导地位正受到Tensilica的强烈冲击  上网时间：2007年09月10日   
http://www.ed-china.com/ART_8800022480_400012_500016_OT_98a8fb3a.HTM?click_from=2100002130,8000022627,2007-09-10,EDCOL,ARTICLEALERT

ARM RISC处理器内核是目前系统级芯片开发人员的主流选择，这在很大程度上得益于大众市场对它的熟识度和由此而形成的庞大ARM内核开发工程师社群，不少客户选择它主要就是因为上述因素，如SigmaTel和上海杰得微电子，记得杰得微电子董事长欧阳合博士有一次曾对笔者说：“我知道其它内核供应商的解决方案能提供比ARM更低的功耗，但对于终端用户而言，电池工作寿命是否短了几十分钟他可能根本就感觉不到，这点差别他很可能根本不会在乎，但对我们而言，选用ARM可更容易地找到熟练软件开发工程师，从而更快地完成软件开发任务。”

不过，如从其它几个主要的处理器内核选择判据（如性能、功耗、流片费用、许可费用）来看，Tensilica提供的解决方案都要优于ARM。而且，在目前的后PC时代，嵌入式设备对处理器的需求越来越趋于多样化，如控制CPU、音频DSP、视频DSP、网络引擎、高性能DSP、特定功能协处理器，它们或者要求低功耗，或者要求高性能，或者要求很大的I/O吞吐量，再考虑到当今日新月异的各种新标准、新协议和新格式的出现所带来的对软件可编程日益增长的需求，处理器定制肯定将变成未来必然的技术发展趋势，而Tensilica是目前市场上唯一的可配置处理器内核提供商。此外，Tensilica不仅可提供RISC处理器内核，而且还是目前市场上主要的二家DSP内核提供商之一（另一家是CEVA）。综合考虑以上因素，我认为Tensilica的发展前景要优于ARM。

Tensilica亚太区总监黄启弘表示：“ARM内核的核心指令有180条之多，而Tensilica的核心指令只有80条，这就从本质上决定了ARM内核的功耗要远远大于Tensilica内核。Tensilica内核的性能与ARM同级别内核相比都要高，而且功耗都比ARM的要低。”他补充道，这不是我们随口乱说的，而是权威的EEMBC(www.eembc.org)和BDTi(www.bdti.com)基准程序测试的结果，你会发现我们的Xtensa可配置处理器的性能不仅远优于ARM和MIPS，而且比TI的C6203 DSP还要高出一倍...
: h! [  c6 c" v" R
4 }+ N8 P* y+ a8 z
生态系统日趋扩大和完善 Tensilica现已建立起一个完整的生态系统，它的第三方合作伙伴现可以为上述Diamond系统内核提供完整的软硬件支持环境，包括：Monta Vista提供的Linux OS支持；Mentor Graphics提供的Nucleus Plus OS支持；Sophia Systems提供的micro-iTRON支持；Wind River提供的Tornado/VxWorks OS支持；Mentor的Seamless产品所提供的软硬件协同验证支持；Sophia Systems和Yokogawa Digital Computer提供的ICE支持；Macraigor Systems、Sophia Systems和FS2提供的JTAG ICE支持；Synopsys、Cadence和Magma的EDA工具支持；Intervideo、Sci-worx、Dolby、CodingTechnology、Qsound、SRS、SONIC Networks等公司提供的音视频解决方案支持；以及Upzide提供的VDSL网络解决方案支持...

hiwu

Tensilica和ARM的市場還是有不同的。
如果要run Linux or WindowsCE還是非選ARM不可。
0 i. \) i  j: t( ?' ]2 y現在的SOC設計的方式通常是，先決定要用什麼軟體，再決定用什麼硬體。

chip123

November 5, 2007 -- Tensilica, Inc. today unveiled the industry’s smallest licensable 32-bit processor core based on an industry-standard architecture. The new Diamond Standard 106Micro core takes up only 0.26mm² in a 130-nm G process and only 0.13mm² in a 90-nm G process. This makes it smaller than the ARM7 or Cortex-M3 cores, yet at 1.22 Dhrystone MIPS/MHz, it delivers higher performance than the ARM9E cores.
7 E) T* `) T+ }
The low-power Diamond Standard 106Micro is designed for simple controller applications in SOC (system-on-chip) designs, and an ideal choice for designers migrating from 8-bit and 16-bit microcontrollers to 32-bit processors. All Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners, who provide support with operating systems, design services, hardware prototyping and emulation, libraries and memories, EDA tools, and peripherals.

“In many SOC applications, the smallest possible microcontroller is all that’s needed to coordinate the various tasks being performed on the chip,” explained Chris Rowen, Tensilica’s president and CEO. “And often in devices that already have one or more other heavyweight applications processors on chip, one or more subsystems need a low-power, low-cost, localized controller. By leveraging our core configurable processor technology, we were able to quickly create this new core with the smallest footprint in the industry.”

3 ~% K! n6 p; uThe Diamond Standard 106Micro is an extremely low power, cache-less controller. It employs a 5-stage pipeline so it can easily achieve 250 MHz in 130G process and up to 400 MHz in 90G process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves a higher code density than other 32/16-bit architectures. Area and performance information for the Diamond 106Micro is in the chart below:
: H3 R) ^7 Z) y/ K9 Q1 L

+ y- r1 g7 a; I! Q% Z0 T
; X# \& Z  [% G8 f8 FWhile it’s smaller and more area-efficient than other 32-bit commercial microcontrollers, the Diamond 106Micro is a fully equipped controller. Using a traditional Harvard architecture, it features separate local, tightly coupled, instruction and data RAMs to eliminate memory contention and provide fast performance on performance-critical code and interrupt handling routines. RAM size is user selectable up to 128K bytes. It features a 32-bit iterative multiplier for arithmetic operations, a trace port for debug, an integrated timer, and a rich interrupt architecture with 15 interrupts at two priority levels for flexible and fast interrupt handling.  The Diamond 106Micro offers performance comparable to other vendors’ much larger 32-bit CPUs in a smaller footprint. For example, the Diamond 106Micro core offers ARM9-level performance and capabilities in a smaller footprint than the ARM7 or Cortex M3 controllers. See table below:
3 C  g* [9 {: h1 [

5 P; F" ]/ `4 n6 C9 f! OData on ARM products taken from ARM public website and product information flyers, June 2007, for TSMC 0.13G process. All speed, power, and metrics are subject to variation based on designer’s design tools, libraries, and fab choices.  AMBA AHB-Lite and AXI interfaces availableAll Tensilica Diamond Series cores are available with the native high-performance Tensilica PIF processor interface, suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect). In addition, designers can use the ARM AXI interface or the AMBA AHB-Lite interface to leverage existing infrastructure and peripheral component sets.  Based on proven Xtensa processor technologyTensilica’s entire Diamond Standard processor family is based on its proven Xtensa configurable and extensible processor architecture, used in over 250 chip designs by over 120 licensees. Tensilica’s engineers used the same Xtensa processor generator technology as its Xtensa processor customers use to create these optimized standard configurations. Tensilica’s automated processor generator technology completely verified the configurations and produced the matching software tool chain. By using the proven Xtensa architecture, customers can be reassured that, if they like one of the Diamond Standard processors but would prefer a more tailored processor solution for their application, they can upgrade to an Xtensa configurable processor and maintain full software compatibility.  A comprehensive infrastructure of tools and supportMany ASIC customers prefer the simplicity of purchasing from their ASIC or foundry silicon provider a processor core as part of the NRE (Non-Recurring Engineering) expense of their SOC design. Fujitsu Microelectronics America, Inc. and NEC Electronics America, Inc. provide direct licensing of the Diamond Standard processors to their ASIC customers. And a network of Tensilica Authorized Design Centers around the world – including leading companies like AFTek, D-Clue, eInfochips, Genesis Technology, HD Lab, IBEX, Magellan Discovery Corp., Tallika, Tata Elxsi, and Wipro – can provide a Diamond Standard core as part of turnkey design services. Tensilica provides a proven infrastructure for its Diamond Standard processor core family. This infrastructure includes software development tools directly from Tensilica as well as:
2 j% @9 j8 z5 W6 I6 M

The Diamond 106Micro is supported by the ThreadX RTOS from Express Logic. The other members of the Diamond Standard processor series support not only ThreadX, but also Nucleus, uC/OS-II, open-source Linux, and micro-iTron. Optional FPGA bitstream and board support package for Avnet Xilinx LX60 and LX200 demonstration boards SOC emulation support from EVE, ProDesign, S2C, Sophia Systems, Synplicity, and Yokogawa Digital Computer JTAG probe support from Bytetools, FS2, Macraigor Systems, and Sophia Systems Libraries and memories from ARM (Artisan) and Virage Logic. Support for popular EDA tools from Cadence, CoWare, Magma and Synopsys Diamond 106Micro model for CoWare Platform Architect available from CoWare.

AvailabilityThe Diamond Standard 106Micro is available now from Tensilica and its partners.
) C  {: [0 p; W" y$ c6 S% O" p% P
Go to the Tensilica, Inc. website for details.