|
|
Software Support
, G: j/ p; _- }6 D) s+ f- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
$ x+ {( w B( k+ h
; q; ~0 P( @" l- G) |- | O3 l4 kPlatform Support 2 c' {& I& `! o/ d+ j r
- Microsoft Windows XP (32 bit) 7 j0 r( X9 K: G+ m6 c4 k# |
9 S* K6 p( S3 u) A7 C
Device Support
, N9 e) m5 x" _4 c- r# G* l: f0 m- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
0 R, v3 o- g: ]& c
2 S' y5 R! o7 w! c; ONew Features
( r, a% {+ u: e% r& c. X/ q1 M9 R& QGeneral New Features and Changes
( L+ Z/ o% _) _6 V- Supports "Create New Memory Part" for all the designs.
! b: {' X9 k% S0 a& X- DDR and DDR2 SDRAM designs for Spartan-3A. # {/ L- Y1 _; ~: ?0 q0 m5 K
- DDR SDRAM is supported for Virtex-5.
8 t! w$ Q1 t _# {1 V, r. P- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.
- H( t ]$ E; d5 t- MIG now pops up the design notes specific to the generated design.
/ b' ^! s! m# k3 w+ J$ v- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
. j1 V; M7 Q/ Y8 N4 j- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. ' m5 k7 b3 Q1 M" Y
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
3 q) x" {, K# d0 I- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
% ]4 P2 Y8 |# G) s" G9 \! d" l- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". # T- b1 _0 R3 F2 T/ ^! @% c
- Default setting "DCI for Address and Control " is changed to "unChecked".
( h# m. F) ?, C, ~3 g( o' {" p- Frequency slider is changed to editable box in the GUI. 3 E, ], |4 a$ s n- v
- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
! g$ @" X$ B* [- Removed console window when running MIG through CORE Generator.
; M- ], j1 O# t; h; t) @; i- WASSO table (Set Advanced Options) accepts only numeric characters. & s! e" k* d C3 G' D) a, ]
- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
, y* ?5 |2 D' e3 ]$ A- Provided web links for all XAPPs in the docs folder of the designs. 7 c* u3 i" Y6 |* @9 \' R
- Provided link to Data Sheet instead of Log Sheet in the output window. 4 {! J5 _4 C7 S$ g
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. 0 X& ^# M2 x' ^. A8 C
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. : B7 N1 {* c+ ?4 e$ b8 J
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
2 R, M; g h! q) `
/ y+ f1 d L' E/ IVirtex-5 New Features and Changes : o( I9 A# G% ?& \+ F5 _ B8 U
DDR2 SDRAM ( \: X! R- g) ?0 ?& t8 c
- New controller with several high-performance features. All the features are described in detail in the Application Notes.
6 b' C3 N9 \4 L7 p; y! m7 `. h- Enhanced data calibration algorithms for higher reliability.
- Q2 r$ _' ~( N1 O! J- Bank Management feature is supported.
" A9 y; E* X- ?! I. ~- Supports VHDL.
0 T2 l1 O. m1 B) }% S C5 F' w- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
& m$ V! w7 l$ p- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. ' r B0 B8 h6 K2 y& q B* g
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. ' W3 J( @0 ]+ M! K' _
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. : {" M* z+ t) }: ]0 R5 y3 h9 E! }
b. WASSO is applied to all the memory interface signals.
8 W9 f- |" m: W3 {7 R, Ac. Signals such as "Error" outputs are not part of the WASSO count.
5 }# }" s1 N2 f" ]& a: F- M
8 M% A0 M \1 F: d% F' MDDR SDRAM ( ?1 K4 w' o- L+ y
- This is a new design for MIG. Supports Verilog and VHDL.
Q: G/ W9 \& b% V: |- Bank Management feature is supported. $ E V9 j7 K" c4 p# U/ y
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. " u1 J) m3 p$ a0 d) c6 H. k9 H( i
- x# G% S9 E. D
QDRII SRAM 3 ]5 X& }5 ^ S: w
- Added support for VHDL.
2 M. F [8 r: X5 V& w5 q8 Q3 B- Added support for 72-bit designs.
) |: F9 N9 R* n+ I" U" }8 g1 v% b- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. , e b. A) B1 I0 g8 _" }
- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 6 @% Q% i" Z) s+ O
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
+ q/ m v( V W( m& e" l& G- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
2 g6 L7 t: N7 l; y! @% p. H# ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 8 V! p) ^/ b4 h1 @1 s
b. WASSO is applied to the output signals only. 3 d0 W+ }# S; } q& L- Z' ], P
4 Y& l1 A2 s, J% s1 c; l E4 MVirtex-4 New Features and Changes
+ m4 ?9 e! u: H! IDDR2 SDRAM Direct Clocking r) A) v( z! x* u4 c5 z2 {- V+ ? ^
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
# ?9 [% x( ]+ o% b- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. 3 I7 k! o: {/ K- v! J) ]
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
m6 D& V# p/ |" ^* O/ }. C- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. 9 o2 \. q+ \6 \( [( {8 u, ?1 S
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. ; W! E% X5 [' q: o6 l: \
- Removed all TIGs in UCF. The reset signal is now registered in every module.
6 r+ x. [- A8 \ N2 M4 B1 f- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
% y2 z- Y; |; L& ]5 R- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. & [7 K1 w8 c; A \! q" x9 `
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. " S! x- ]: A. t, x8 d+ o
- Replaced `defines with localparams for Verilog.
3 R! _. x; p( u7 T- S6 W3 k5 d8 d- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
7 V1 o: F# @! P* f- Several state machines now use "One-Hot Encoding". - R7 ?% Q3 v5 `: `$ B6 t2 K! Z
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
" Y$ |! O! f) }9 E3 C" r% ?2 e0 U- Signal INIT_DONE is brought to top module.
; T- R( U" F2 r' c* y- Removed the UniSim primitive components declaration from VHDL modules. : W! e. W& A {# y5 n
- We now support all multiples of 8-bit data widths even for x16 memory devices.
5 K/ ]$ t k# g' S# c- We support memory devices of speed grades -3 and -667.
% b) m# x0 ^+ N- W. {0 _- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. - u: m2 [! J: {' f
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
. u* l2 y C; r$ q3 Fb. WASSO is applied to all the memory interface signals.
6 b5 O+ q8 u3 s$ T8 |7 d' Oc. Signals such as "Error" outputs are not part of the WASSO count. / l/ ^; }3 |; } e0 R
) Z$ E! m" s" ]2 P: w9 A; pDDR2 SDRAM SERDES Clocking
# U' A: R1 C9 p/ Q0 b/ u- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
/ u6 K3 y' M+ `& o0 t) R- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
9 B) {/ [ c7 d; N6 r- Support for ODT.
3 [! k4 T, X/ P7 k- W0 B- DQS# Enable is selectable from GUI through Mode registers. ; |6 R. V j8 e
- Removed all TIGs in UCF. The reset signal is now registered in every module.
: G3 [9 q# y) y5 r. L: V+ C- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
; f1 B! a8 X% f- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. / U' N+ O J2 o9 P
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
# t: f/ @) h: t: b- O% @' z7 V- Replaced `defines with localparams for Verilog.
; b6 Y8 `' U! i' ^2 K. r- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
6 N% q2 x5 V6 l* n( T$ m" z) K, r7 x- Removed the UniSim primitive components declaration from VHDL modules. % B% c9 y: u( O' E p
- We now support all multiples of 8-bit data widths even for x16 memory devices.
0 z3 W# ?" M& _, f, h- Signal INIT_COMPLETE is brought to top module. 3 t' C% J8 O! m& G7 S N
- Memory devices of speed grades -5E and -40E are now supported. 4 X. F8 }) n ~: z9 C
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 3 P$ S8 \4 @9 p: i# m
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
! V2 Q4 v: h* P+ r" l5 ^- Ib. WASSO is applied to all the memory interface signals. % e) \( O7 c' }8 w2 W" m
c. Signals such as "Error" outputs are not part of the WASSO count.
5 _' ` d c" V: U" c. W+ ~. L, m0 U, @$ K
DDR SDRAM * ~8 J: W, o) x _; T
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ! @& k1 `) s* t8 r I' ^1 Z
- Removed all TIGs in UCF. The reset signal is now registered in every module.
1 E" E1 P: N( V1 o- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. : a5 e! U- w* K( Q- g9 J
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
D6 N) m) R4 D0 V/ ~ v. n6 z7 f- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 2 X9 t, b5 x! E* @( Y
- Replaced `defines with localparams for Verilog. ) F @' G2 h) K( |
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
& n' A4 L2 P s' ^" J8 z- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
0 c E2 j5 M. s& O" G6 |0 }- Removed the UniSim primitive components declaration from VHDL modules.
/ P' x0 a7 p9 x- We now support all multiples of 8-bit data widths even for x16 memory devices.
7 r& L. u) y3 k5 s- m( o- c9 G A- The signal "init_done" is now a port in the top module.
8 v! P" w' N4 {5 X; m- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. : G3 U( q9 S; T2 ]" b
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
. P7 ?+ P- u% [! Y- I7 m k' W1 `0 D% |b. WASSO is applied to all the memory interface signals.
* d3 S7 B9 N6 u& G* V+ {1 qc. Signals such as "Error" outputs are not part of the WASSO count.
5 I, z4 U8 x6 _! \: ~* {
. C. l# l$ y+ l8 M" r3 `RLDRAM II 1 ], u) L* J) e6 c
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
6 o& F* C# g/ ]; U/ m$ h( W- Removed all TIGs in UCF. The reset signal is now registered in every module. - X. b1 }) x7 L8 @9 m
- The design now uses CLK0, instead of CLK50 and div16clk.
0 B& \# i2 P; O) V# ]- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
* U0 d9 m' Y) U" c/ ], t, W- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. 6 P0 e# H2 W% n$ J8 W; @% d
- Removed unused parameters from the parameter file. ! e2 f0 f8 A$ L$ A% [9 G
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- N0 C$ z% E6 w- W5 Q- Replaced `defines with localparams for Verilog.
9 X9 z( c9 K( E3 q- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 4 {: x% y/ q7 O) L( C) O
- Removed the UniSim primitive components declaration from VHDL modules. ! _* U( y+ I K+ j1 @9 ~# X0 L
- The signal "INIT_DONE" is now a port in the top module.
! m) D$ \) ^+ G9 h- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. ! ?0 ]" {% J( e9 [
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
3 a5 J' _6 P- s0 x b- D' N- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file. , @6 ?2 S4 U( Z3 g# A4 r4 M
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
1 h/ P% \( b$ k- I' B1 Ka. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ) q0 L. O0 ]" F' _/ [0 q6 C
b. WASSO count is applied on output signals only for SIO memory types.
5 O& U( s- \0 Pc. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.
! A8 v% \$ ^ m% K0 b8 l2 {9 c6 R, M; B0 l7 d. O5 }$ a
QDRII SRAM ; `* _- `( i j
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. % [4 Q/ H6 W4 n7 e# K) ^
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. h8 J* |: p: Z! d/ M
- Supports generation of designs with out DCM. 4 p+ c! l) f3 G3 ~7 U& c" W: y; n
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. # p7 C$ g0 a' f$ [' D) _
- Removed all TIGs in UCF. The reset signal is now registered in every module. - l7 {# N7 F, P% `+ t# ^7 t2 x
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. $ P6 C* o- N1 q0 g
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ! M/ V, I+ t, q/ b0 G
- Replaced `defines with localparams for Verilog.
8 T5 L" J7 K% B+ N- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 8 z- [, a! R3 v9 B4 q, T
- Removed the UniSim primitive components declaration from VHDL modules.
! y% T- U' y% |0 e- The signal "DLY_CAL_DONE" is now a port in the top module.
% f" z$ J# c% m7 `) F- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 1 M! |6 _* P( ]$ j8 G
- Added support for DDR Byte writes.
1 M5 J3 @. M' x0 }, o2 Z- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
) e O! E% e n9 {' Xa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
, k% N1 `. r" p0 |5 |5 N5 W7 Wb. WASSO is applied to the output signals only.
! a* p3 n( M# w+ h- Dc. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. ( M5 e0 A. f3 G2 n5 C, W3 Y
8 B0 |$ Q5 [$ b" R K2 {/ EDDRII SRAM
8 R$ o. {! b$ o, K- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
' D. a* @- L( P5 I6 ]5 k5 Q2 O3 M, B- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. 2 n6 Z8 r" c( s" s. V% j
- Supports generation of designs with out DCM. $ P0 ^. B0 C1 f* H9 I: c
- Part CY7C1526V18-250BZC has been removed from Memory Parts list. + V( I& F( s! G& H, }+ B2 L
- Removed all TIGs in UCF. The reset signal is now registered in every module. 3 n5 a) l+ u& D( o
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 5 N. S8 `4 q' R3 w
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
! f: x: o$ K8 Z1 ]; M* h- Replaced `defines with localparams for Verilog.
! ^* V7 m& G& ]2 P0 M( z( }3 x- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ( R( i$ w8 U# L) u5 i
- Removed the UniSim primitive components declaration from VHDL modules.
( `5 f2 e% M: N( t- C0 x) Y" q% F- The signal "DLY_CAL_DONE" is now a port in the top module.
& [0 x D" I" z; q- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 4 E, a3 H& r0 t2 m) X$ x2 o
- Added support for DDR Byte writes. 3 f* P2 c( l" M* p" |+ O
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
0 q- ~ B1 l' }" M" K5 ra. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
- M7 \8 W) h1 I% @4 d7 [b. WASSO is applied to all the memory interface signals.
0 P4 R6 l1 k" s& P j2 oc. Signals such as "Error" outputs are included in WASSO count. |
|
IP卡
狗仔卡
發表於 2007-7-24 12:23:39
QQ好友和群
QQ空間
騰訊微博
騰訊朋友
收藏
分享
頂
踩
分享
提升卡
置頂卡
沉默卡
喧囂卡
變色卡
搶沙發
千斤頂
顯身卡
樓主