free DRAM controller~~~ MIG

tommywgt

Software Support
6 I9 g! e6 f9 _5 o- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.

+ t# W3 s4 _  h  v# k( C! g8 sPlatform Support
) |6 e' C& u* z9 u8 [- Microsoft Windows XP (32 bit)

Device Support
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.

8 \3 ^* O9 K' v5 TNew Features
General New Features and Changes
: w) K. J4 A9 A& b9 h4 p& X2 |& N- Supports "Create New Memory Part" for all the designs.
- DDR and DDR2 SDRAM designs for Spartan-3A.
9 h3 w- l2 B1 K2 [9 e# j0 j# G- DDR SDRAM is supported for Virtex-5.
, F" h+ K$ o% j$ _) x- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.
- MIG now pops up the design notes specific to the generated design.
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.
# D! A/ D& a% `5 u( Q- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
6 h! k0 [4 }- l* Z8 \! K* m. ]- Default setting "DCI for Address and Control " is changed to "unChecked".
- Frequency slider is changed to editable box in the GUI.
- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
* U# N; {; V6 M! q- r- Removed console window when running MIG through CORE Generator.
- WASSO table (Set Advanced Options) accepts only numeric characters.
- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
- Provided web links for all XAPPs in the docs folder of the designs.
) J+ o9 B$ c$ a1 i. Z- Provided link to Data Sheet instead of Log Sheet in the output window.
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
) j/ H& h5 }. U. v: }- X# ^# Z- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
6 {& I) Z7 ]4 c, l. Z( e: ?
. M& T7 a* l7 ]9 b: N. A+ z- J7 `Virtex-5 New Features and Changes
DDR2 SDRAM
% A- G' E% x3 ^/ D* N7 j; I5 P! [- New controller with several high-performance features. All the features are described in detail in the Application Notes.
- Enhanced data calibration algorithms for higher reliability.
$ J! \; Y& ~: x5 K  m  A- Bank Management feature is supported.
- Supports VHDL.
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
' T- z. ], ?& J7 {6 f" W- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
b. WASSO is applied to all the memory interface signals.
c. Signals such as "Error" outputs are not part of the WASSO count.
4 @" S& ~; E+ m
DDR SDRAM
- This is a new design for MIG. Supports Verilog and VHDL.
9 w0 ?) y; z# `6 j- Bank Management feature is supported.
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear.

6 M2 k9 y/ o* e+ }& N4 }9 uQDRII SRAM
! c, q) g/ H1 ^1 y$ L! e- Added support for VHDL.
- Added support for 72-bit designs.
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
) g) S+ |. F: e# u$ y( U# z  la. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
0 d- H0 }- R6 @# a# ~b. WASSO is applied to the output signals only.
# [' s/ O% [' q9 v# f3 i
Virtex-4 New Features and Changes
DDR2 SDRAM Direct Clocking
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
  \# ?7 f- X% \: f) n% b* Y. N- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
4 e: i# ^. ]. i" h( ]6 B& V2 x- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
  u1 i2 S+ }' _- v: s2 }" h& r- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
/ \- }/ x, e* o: ~: f2 m' [6 }- Removed all TIGs in UCF. The reset signal is now registered in every module.
( _! c. u5 {) v0 F( H: i- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
. x; x6 ~# Y. {; ?# L3 }5 m4 ^- Replaced `defines with localparams for Verilog.
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
- Several state machines now use "One-Hot Encoding".
3 T6 _- h9 G7 A4 S9 P- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
. Y% D4 V: O* P* T- Signal INIT_DONE is brought to top module.
% Y& ]7 B+ J" Q. X* F% R, B- Removed the UniSim primitive components declaration from VHDL modules.
- D& \/ `5 _& e4 `; ^" C: Y* H- We now support all multiples of 8-bit data widths even for x16 memory devices.
2 `0 R  J6 d1 Y$ V- We support memory devices of speed grades -3 and -667.
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
6 _! J5 n$ @0 v8 g+ M  L* n, M6 [/ Ta. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
0 m3 C# S( p/ D: U& J5 w1 \- n8 Wb. WASSO is applied to all the memory interface signals.
0 H; ]$ C# }* ic. Signals such as "Error" outputs are not part of the WASSO count.

DDR2 SDRAM SERDES Clocking
$ c  O( j  y( B& M- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
6 w( F( L' C( ?0 ?  ?; K0 J- Support for ODT.
- DQS# Enable is selectable from GUI through Mode registers.
* \) V# B" j  r6 `! r- Removed all TIGs in UCF. The reset signal is now registered in every module.
, |% g, x2 O" w& h! N" b& R$ w- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
' P0 L7 R, W9 D( H: j- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
' g) V, {- |$ X- Replaced `defines with localparams for Verilog.
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
- Removed the UniSim primitive components declaration from VHDL modules.
- We now support all multiples of 8-bit data widths even for x16 memory devices.
- Signal INIT_COMPLETE is brought to top module.
- Memory devices of speed grades -5E and -40E are now supported.
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
2 ~; s8 ~0 w, K; q( q5 _a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
! t0 Y8 w6 d: x3 I2 ?b. WASSO is applied to all the memory interface signals.
c. Signals such as "Error" outputs are not part of the WASSO count.

DDR SDRAM
. O, A7 i% U8 b& f0 E% Z0 d- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
) u- T# K, T5 Q' q7 X- Removed all TIGs in UCF. The reset signal is now registered in every module.
# c8 L5 f: r; U4 z/ D' p8 h- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
. S' W; j/ t' s; V. p/ P' U; N% x- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
$ X/ I! }4 }5 m! a/ Q- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
5 r: C9 ^- v9 c  m- Replaced `defines with localparams for Verilog.
6 e' g( T7 {$ J3 b6 I, u+ ~9 f6 ]- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
- Removed the UniSim primitive components declaration from VHDL modules.
+ U1 b: L# ?2 B! ?9 X" Z0 d- We now support all multiples of 8-bit data widths even for x16 memory devices.
$ R& W! f' Q' @- Y- The signal "init_done" is now a port in the top module.
- e9 L" ?0 k, M! Y9 u+ e2 p1 D- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
b. WASSO is applied to all the memory interface signals.
c. Signals such as "Error" outputs are not part of the WASSO count.

' t# m1 w  J1 R0 ?0 o% gRLDRAM II
1 q3 b7 @  R, k0 {% C( A. ]) z* t- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
- Removed all TIGs in UCF. The reset signal is now registered in every module.
- The design now uses CLK0, instead of CLK50 and div16clk.
- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
( b: @* T* W3 |+ A& \3 x2 c& ]7 {- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
- Removed unused parameters from the parameter file.
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- Replaced `defines with localparams for Verilog.
# E  b  i6 J  r/ \& g: M8 @- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
- Removed the UniSim primitive components declaration from VHDL modules.
- The signal "INIT_DONE" is now a port in the top module.
5 K( A, n9 E1 F& a! H# R- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
' f  m6 O# L, S( S- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
" Z* i( d! x  Z- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
b. WASSO count is applied on output signals only for SIO memory types.
c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.

. ~! u$ F: H$ gQDRII SRAM
) e7 C9 Y( o7 V. y0 k* U, ^2 n- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.
0 j: z& k. t0 {" V- U! w) \- Supports generation of designs with out DCM.
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
- Removed all TIGs in UCF. The reset signal is now registered in every module.
! q+ q* M9 R* Q( \) ?# k; @- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- Replaced `defines with localparams for Verilog.
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
3 q- k" S! Q9 `/ m0 X/ ^* `- p% y5 e- Removed the UniSim primitive components declaration from VHDL modules.
- The signal "DLY_CAL_DONE" is now a port in the top module.
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
- Added support for DDR Byte writes.
8 W0 k% x& {2 @0 u  X. B- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
0 T$ h, G- Q  {b. WASSO is applied to the output signals only.
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.
7 A# }, J  R: [% Q% j7 B- y/ ]! b
0 T/ |8 g# {3 J9 h1 B0 h7 ODDRII SRAM
' m1 o6 K$ u: X5 h: m. R( S- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
* f% G/ w& j' U. f- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.
  q" i/ t# _/ P$ L: |% S, j* w' Q/ f& r- Supports generation of designs with out DCM.
7 N3 {( ^) @# H- Part CY7C1526V18-250BZC has been removed from Memory Parts list.
- Removed all TIGs in UCF. The reset signal is now registered in every module.
9 p) H4 S: s* J, |- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
) s5 l4 T# e  [7 ]$ C2 K$ Y8 m( {- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- Replaced `defines with localparams for Verilog.
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
- Removed the UniSim primitive components declaration from VHDL modules.
- The signal "DLY_CAL_DONE" is now a port in the top module.
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
  L% y5 t4 o/ {2 K( e" L1 C2 G- Added support for DDR Byte writes.
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
) S8 ~+ N% a7 H* N" I7 _- U; Aa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
b. WASSO is applied to all the memory interface signals.
c. Signals such as "Error" outputs are included in WASSO count.

tommywgt

太長的東東沒人想看吧!
* x' [5 u' o  r4 M) L
2 Q4 l8 Q* H2 k總而言之, 這是一個由Xilnx提供的free IP, 用來控制memory用的, 目前都拿來接DDR/DDR2 SDRAM比較多
( `. a) r* t2 @( D1 o3 [$ L+ g
很好用哦

steall74220

請問我現在用CORE產生出來的MIG是直接燒在板子上使用嗎??

tommywgt

基本上是的
  V7 ~& F8 a, \, {+ B7 \  B( g
實際上當然要跟你自己的設計整合一起才會動

anita66

沒有載點呀??這是說明文章而已嗎??我想要下free IP呀??

qwe11197

剛剛看了一下簡介
. N& x; G2 L8 [感覺蠻好用的軟體
% D0 r" P, u1 {結果沒有載點真可惜
自己去搜尋一下好了!!