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Software Support / I4 ^" b& r' e: X
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
+ ~. K2 |* {: i0 O: R4 N0 m" z6 s: G6 J, Y) f8 x" ?6 A9 |7 I& V7 h
Platform Support . Z5 H/ u: F- m2 Y8 s8 R! ?$ |& Q
- Microsoft Windows XP (32 bit)
& ~/ o: Q; g6 Z; c3 S: _8 b5 x5 ~0 |9 U) f$ @: |( J
Device Support - }! Z: B5 b7 k! X0 S& m' V, t
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
+ p# Y# K/ d! z' n8 f: A' A+ n2 S' q5 S! U8 ]7 Y+ F
New Features
; T# ~$ D9 m, R& V( Q' PGeneral New Features and Changes ! \- s: M) t0 Y G, ^
- Supports "Create New Memory Part" for all the designs. 0 Q, t- G3 M) U8 V& T' o/ v9 u
- DDR and DDR2 SDRAM designs for Spartan-3A.
$ E; c. F7 B5 E" T. ?) M- DDR SDRAM is supported for Virtex-5.
4 J0 V7 e4 @; @$ H2 B- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. * H# z7 h7 k$ A0 @
- MIG now pops up the design notes specific to the generated design.
) G$ Y. h# e0 \$ D- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. # l8 q- S7 k$ k& l8 }2 A
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.
+ T4 A+ k* ]- h" t- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. 6 @1 \) E+ C W: t& E
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. * g8 m9 x6 g* J3 g
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
, z" n1 E- G8 c' c+ U- Default setting "DCI for Address and Control " is changed to "unChecked".
: a' a, b0 K0 ^- Frequency slider is changed to editable box in the GUI.
) y0 e. w2 K0 X0 b; i! T- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
5 y5 S$ X1 m. `" R5 h- Removed console window when running MIG through CORE Generator. # X1 L- L I7 K! `6 O; [% R
- WASSO table (Set Advanced Options) accepts only numeric characters.
2 @% H5 H) f- H- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
$ H! M$ r! e& q- \- Provided web links for all XAPPs in the docs folder of the designs.
& z/ R* |' w* a8 u- Provided link to Data Sheet instead of Log Sheet in the output window.
7 v! ]* Y+ c3 \ f R U4 j, O; h- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
) S: I" J) d0 o- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. m: P7 H: s! M9 ?7 v
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. " }+ h" S: U7 t, l% j
( ?( N; N; K2 z8 j" E' t0 h! x( _6 X
Virtex-5 New Features and Changes
8 \' X2 Q$ D4 \8 P* ?DDR2 SDRAM ; E. E* D! s$ a+ i4 }% H* u
- New controller with several high-performance features. All the features are described in detail in the Application Notes.
+ i7 [1 \" P& p* M6 O. J& J; J- Enhanced data calibration algorithms for higher reliability. ; L# n# x% q* [# D: U3 o2 ]/ W
- Bank Management feature is supported.
4 z/ w2 H7 j6 s$ C8 c; `3 w3 \- Supports VHDL. 3 T2 C2 `4 u7 \
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
7 k4 {9 z) o5 W' A- @1 r- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
" h% n3 e/ V( s. ^- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.
+ j5 ]: c3 r9 Y% T6 T z: @7 ha. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
1 E5 N( o1 \+ \& j9 U) Cb. WASSO is applied to all the memory interface signals. W5 K; [7 _5 s: i _) p0 e
c. Signals such as "Error" outputs are not part of the WASSO count. , m* K0 A8 }5 }! ~2 [. ~
6 N3 v6 W- e) p- m! gDDR SDRAM - A6 c: G# |/ {& q3 g5 a
- This is a new design for MIG. Supports Verilog and VHDL. / M; z0 K& b' A- {" j" u
- Bank Management feature is supported.
$ @: }* ?+ _% d6 M- G2 z- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear.
. U( l- j1 v4 v2 g
8 G6 s6 E+ y. O/ F" n0 x0 ]8 o/ w) @QDRII SRAM
& m" n0 O0 e7 a }, y$ A- Added support for VHDL. 9 l' S& f0 F' `, ^7 g1 Q) r
- Added support for 72-bit designs.
8 Q. K" m8 |" n- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. # H/ ?) |2 n4 p) b6 u& H
- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6
& p: C( Y' I+ K, ]2 F- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. [+ W7 R1 d$ g8 s
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. & e/ U7 l# @2 q9 ~, U" ~' E1 A3 T
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
8 g2 A" T/ T: Ob. WASSO is applied to the output signals only. 7 J( L0 @. y- }% J2 _
# u9 Q% i8 F0 |Virtex-4 New Features and Changes
8 j2 [- i! H) q8 x; v' q& rDDR2 SDRAM Direct Clocking
/ T0 h7 b& y; Y3 X* O- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
5 u- y) g3 r& @9 X- Y/ ~0 w- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. * J$ y/ s* p9 {
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 0 I0 `4 a7 v* ]
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
$ c4 f/ L4 e4 h9 x- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
3 L/ v) y& J- I7 e! m! ]* a8 d* i- Removed all TIGs in UCF. The reset signal is now registered in every module.
8 w, L' {6 Y; p! C( u1 ]2 i- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 9 C; }7 l& r$ S* ^2 }7 a$ o
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. * \9 f: j( ]8 s3 |
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
3 v* A2 N( W: M: P$ }- Replaced `defines with localparams for Verilog. B0 i3 |9 D: q0 n$ c- d
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. , G% ?" I7 v9 _ u* ~$ r% s
- Several state machines now use "One-Hot Encoding".
8 N( G \9 E5 \1 @- o, i- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
4 Y% B' C, ? b8 g- Signal INIT_DONE is brought to top module. 4 m3 t' R4 U2 e( e
- Removed the UniSim primitive components declaration from VHDL modules. 6 m& i7 V1 x) L- G5 I) J
- We now support all multiples of 8-bit data widths even for x16 memory devices.
8 i) z* V0 |2 @; P# R$ N9 C$ p* |2 \- We support memory devices of speed grades -3 and -667. 4 h+ b* c" I. `1 o E6 p
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
- K! Q8 T+ O8 Q5 ]; j* va. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
4 T% x5 y; p1 l$ ]$ x: eb. WASSO is applied to all the memory interface signals.
$ a; T( A6 R* k/ q4 G5 u. _) sc. Signals such as "Error" outputs are not part of the WASSO count.
8 S7 {0 E, X$ U% M/ k
- w9 n ]6 Y9 P) t7 w- sDDR2 SDRAM SERDES Clocking
2 ]4 z! x) Z' f5 Y3 w7 H8 I! l- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. / y' A6 ]6 N7 V1 m, i
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 7 k5 V: H A/ U
- Support for ODT. $ o& K7 t! A' k' P% F$ j( n
- DQS# Enable is selectable from GUI through Mode registers. 6 [' f! v4 r7 j0 u0 o2 N
- Removed all TIGs in UCF. The reset signal is now registered in every module. + C# t7 _( J2 L: B$ Y. F
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
$ f4 {+ }: ^4 c$ w) f* z; G- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
* G" R; r( Y \- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ) O! d" B! ]# c% E
- Replaced `defines with localparams for Verilog.
/ p$ H: L% |1 J( q* A9 T3 C7 H- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
. F8 F: ~1 j% _- Removed the UniSim primitive components declaration from VHDL modules. 4 D9 e1 J& R+ C' M. q* c5 l
- We now support all multiples of 8-bit data widths even for x16 memory devices.
6 Z0 V6 h9 M$ m* v& e f: z7 r- Signal INIT_COMPLETE is brought to top module. ( Z+ S/ j. W7 o7 O, `5 M4 D
- Memory devices of speed grades -5E and -40E are now supported.
4 Z6 F( V r T6 q- |- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ! Q1 y3 a: }1 C2 A( @* ^5 O
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
: B: D1 K }% G/ b0 v+ Hb. WASSO is applied to all the memory interface signals. - A6 n% ]( s: b' \! T
c. Signals such as "Error" outputs are not part of the WASSO count. 7 f" R) o+ r R1 X! P w
* X5 H/ m! X# a" v* F2 WDDR SDRAM
, J% {: B I+ N( P- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 5 A, u: p6 |/ |0 b: A( r
- Removed all TIGs in UCF. The reset signal is now registered in every module.
; C: _/ Q# s0 h2 l- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ( t' u. m0 @9 r) @ s: `2 P; u3 J
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
* c* m- `6 o8 ]6 a7 D. R3 i" E- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
4 y0 m7 _$ k. X2 d- Replaced `defines with localparams for Verilog.
) V( n/ g7 c6 x# i- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
3 X8 B4 u" r. M1 N- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
+ f3 Z( ?' e7 E$ c8 \# O- Removed the UniSim primitive components declaration from VHDL modules. ! v8 q9 j/ I- ~- t1 ]
- We now support all multiples of 8-bit data widths even for x16 memory devices.
8 x+ K( ~7 [+ s- k- The signal "init_done" is now a port in the top module.
% r1 R. p- x! ?1 f. _' a2 Y- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
) r* u" C3 s" `! ]a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
# }* G5 ?/ ~ [4 F. |2 \b. WASSO is applied to all the memory interface signals. $ B1 w( {& t7 _1 i
c. Signals such as "Error" outputs are not part of the WASSO count.
" W8 y( V" C& F/ d. G3 {' |3 n1 q* J$ N4 {- q4 Y
RLDRAM II
. E. d5 D" P# f) W* J- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
( p% `6 m$ P! m7 {- Removed all TIGs in UCF. The reset signal is now registered in every module.
% q. p; j! E' Q+ E8 b8 n. {- The design now uses CLK0, instead of CLK50 and div16clk. + W: V! A3 b: s6 k
- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
8 U3 ?0 {4 J& d0 s4 `5 i% E" z- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
% O# ?+ s! i: t* q0 J. g5 ^! f- Removed unused parameters from the parameter file. 7 G T! L+ @* C8 N% s- F4 s
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
. t' j" r) o2 D# L' H- Replaced `defines with localparams for Verilog. 5 W$ G) w& b# v9 v9 Q+ N) H
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 1 \* S! R* E/ N) q& ~
- Removed the UniSim primitive components declaration from VHDL modules.
6 B2 Z7 {8 k6 t9 T- The signal "INIT_DONE" is now a port in the top module. 7 I5 R, r5 M$ r1 d
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
6 d9 X M4 y' A6 s- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. 5 |. ^# h5 G" p9 h: G
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
, ~4 N' Y* L: x* r6 X* N& v- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
# S1 i( M) E# E/ i% U: g% m, ea. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 6 R* K* Q& _$ ^
b. WASSO count is applied on output signals only for SIO memory types.
! w# I: I3 y5 {c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.
9 P& \9 d/ A7 U' H/ _$ M8 U3 L: {) x9 W/ g9 L: r+ @ U
QDRII SRAM ) E5 I8 Y" n# _) }. _$ }" d
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
! C/ p- Z3 m5 |" E$ u5 {- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. 6 y* U3 v7 q! l+ {. S) |
- Supports generation of designs with out DCM. + Q7 E# o9 h! u2 Q
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
+ k @' j. u. S. a1 C- Removed all TIGs in UCF. The reset signal is now registered in every module. 4 k0 D" ~! {0 `' r) Z1 L
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 8 G. b% O2 r8 } R- q- i
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 4 @* D' }( z8 ^6 G1 n
- Replaced `defines with localparams for Verilog. + x: k5 B1 g0 h3 y$ j6 R
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
+ f1 F3 l- q3 B# A1 I" R. j! @" E- Removed the UniSim primitive components declaration from VHDL modules.
, f$ H+ [ l3 o8 v1 U! m% G; k- The signal "DLY_CAL_DONE" is now a port in the top module.
3 a% j8 t& A$ I8 m. r, H$ F! D- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 8 l6 j$ R0 y2 u* C# J
- Added support for DDR Byte writes.
! }- L7 \1 M& q4 A5 R3 Y: l- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
, T- X4 h0 M, A6 V: @0 v Wa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ) C, S' }+ F+ q' w# N
b. WASSO is applied to the output signals only. : l4 \9 j7 m6 s- h2 ]+ G6 E( A
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.
2 [9 F! `7 |3 }: n0 j9 V: c3 R; a8 x/ u5 u5 Y# Y9 M
DDRII SRAM 0 w7 x& W9 {' t: M2 k9 q
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
* F; {- U; z, S8 J! c; u, f- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.
7 x7 ` R( A# C- B- Supports generation of designs with out DCM. $ U: D; U" f6 M9 w R
- Part CY7C1526V18-250BZC has been removed from Memory Parts list. 5 l F7 i% W$ p" `' Y
- Removed all TIGs in UCF. The reset signal is now registered in every module.
6 Q; [8 f: M, q1 T6 k- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 2 \5 {' D& d: @) p2 e5 O0 h W
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
4 w2 q1 K! v0 G$ v0 ~- Replaced `defines with localparams for Verilog. D% r# q0 E) m/ a- c8 N7 B
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
" ^) S* Y7 R. g1 F/ Z7 {1 V- Removed the UniSim primitive components declaration from VHDL modules. 4 ~2 X" {, u) {4 l6 z4 P" }
- The signal "DLY_CAL_DONE" is now a port in the top module. ( s8 i" U5 Z3 U9 E
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
- Z) `/ m0 H- B6 \- Added support for DDR Byte writes. / {. D. s1 [1 W9 t0 r/ ]
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
4 @5 H h& l0 o! D. J: Na. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
: C' t% d3 e5 m6 ~8 z( }b. WASSO is applied to all the memory interface signals. }" j" j; |' W3 z+ c. Z& U
c. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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