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Software Support i6 Z: W# z( x6 Q, s/ M
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
) W$ E- X/ G, }& k# G- m5 t) z; t
Platform Support $ _/ S. v6 m7 D+ ?
- Microsoft Windows XP (32 bit) + R. @7 A W m- O5 K
# I8 Q- p* K% M/ g, I- a# D
Device Support 7 x% h6 E b6 d! E4 j
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. ; Y# p3 Y8 s- \/ V
' E" A5 Q5 A+ c9 g# }
New Features
0 r( V% J6 x" x0 w) \* k& s* `8 NGeneral New Features and Changes
- b7 J1 n9 A6 Z, T1 D- Supports "Create New Memory Part" for all the designs.
4 {2 |2 A* N7 i4 {& v- DDR and DDR2 SDRAM designs for Spartan-3A. 6 l. c* Y) A7 Q9 ]; o/ b# `0 M
- DDR SDRAM is supported for Virtex-5. % E$ Q2 m+ w- Z, J0 [
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. / O% \- a3 D" F( g- D$ ~
- MIG now pops up the design notes specific to the generated design. ) e7 Y4 N W0 u% q& ^: |- d3 R
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
2 w! t0 U' F6 i- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. ! }8 R2 | K x! A, P
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. 3 e- _! J% y" L8 Q
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. & n' C \0 L" x+ F+ g6 I- { l
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
. B$ m' o9 a: e- Default setting "DCI for Address and Control " is changed to "unChecked". ( D, u; K+ S! k8 [' g
- Frequency slider is changed to editable box in the GUI.
; A; Q' w% T2 m4 u& l5 E( b C- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names. , j# C, H& m. H* M) B2 q
- Removed console window when running MIG through CORE Generator.
. C1 a8 F9 M7 Z* Q, Q6 y- WASSO table (Set Advanced Options) accepts only numeric characters.
9 m- s: k J# |8 @- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. ! u$ J: T |7 i s8 f) q
- Provided web links for all XAPPs in the docs folder of the designs.
3 V9 {: G) O- M( N& A5 L- Provided link to Data Sheet instead of Log Sheet in the output window. 3 D2 ~1 j$ ~5 P) [2 r" c
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
3 c1 Q+ b6 C9 X. i- p' W" J& e- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.
9 u `/ ~7 k; m8 ?9 \- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
. O( _& C5 }+ }; `9 d2 |( c" [' b. X% N& v+ E* s
Virtex-5 New Features and Changes
& E9 C5 y7 B* }. m- u4 YDDR2 SDRAM 5 b! f: b4 J- I4 |7 E! o! G, y# ?
- New controller with several high-performance features. All the features are described in detail in the Application Notes. & A2 D9 N9 _3 j2 q( t' O# K1 Y
- Enhanced data calibration algorithms for higher reliability.
' q/ X" U. r: A5 \' b( H- Bank Management feature is supported. 6 h7 h# X" N$ `5 G! K
- Supports VHDL. - o% C4 V; D( `+ H/ H/ I8 c7 m
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. + Y8 _7 W R+ q- L6 I+ k
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. 7 C. R# t. T# v* j% `0 ^; a
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. 3 N2 [& x6 v9 T
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
7 i% p) ?% N& D. b2 Q" d2 |; Kb. WASSO is applied to all the memory interface signals.
; K# \- q1 H T! H3 v1 N/ Kc. Signals such as "Error" outputs are not part of the WASSO count.
5 E3 v8 [' n V9 e" e/ A
8 X8 ?. P' ~# w1 T3 bDDR SDRAM
( ?+ s& Z: T. P/ M0 R- This is a new design for MIG. Supports Verilog and VHDL.
3 Y& [) x2 x- ^$ D2 t6 ~7 T- Bank Management feature is supported. g4 g/ }7 r' |4 W/ p; o
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. % D) k8 c, i( g& C( x; f
3 V* \" i; H6 H& h: B8 N
QDRII SRAM
8 R+ D5 P5 F: \, x5 L8 D- Added support for VHDL. 4 Y# e* y9 U* ^: G: M+ J; Z0 s
- Added support for 72-bit designs. 0 Z3 p2 X; W5 o/ \5 @+ [: ^1 M
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
( q$ y8 X- b- ?$ j- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 8 m/ [; z" ~1 Q. K7 o o
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
2 B( e% |& `% U$ I7 R& y- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. . I, ^, J {. J
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 2 R% l4 s0 O0 o& I, I
b. WASSO is applied to the output signals only.
9 }8 u2 Y7 r! v+ l
; k6 b" T5 E3 CVirtex-4 New Features and Changes
4 Q" M! }% G8 sDDR2 SDRAM Direct Clocking 0 Y0 n- ^5 f! P0 t- S
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
- o3 r0 e: z- S6 j1 i% S9 }# y! |- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.
7 [, k4 j/ P' {$ ~- ~8 k* Q( `- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
" T5 H# t, `% A/ j- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. : m1 f; M _- _" z) _2 I
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. 5 m- Y3 ^( ?; X7 Z
- Removed all TIGs in UCF. The reset signal is now registered in every module.
0 R) |6 @2 a) Z2 |3 ^- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
3 F# n: i' ]- v: j- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
, j; ?3 n! d6 N3 d- Y3 r3 j- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
. {/ [) E/ @2 w# K% O8 k( `! J- Replaced `defines with localparams for Verilog.
1 a/ n' `" K S9 _9 N9 R+ Y5 S* x, w; f- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
P# l: c3 m: L* r- Several state machines now use "One-Hot Encoding". ( Y* c/ T/ I E B: }# V" V
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
; ?, }- A( t. ?8 {1 t& P- Signal INIT_DONE is brought to top module. 9 l! l9 y7 T* r, a
- Removed the UniSim primitive components declaration from VHDL modules. ! C( N# c7 Y4 Q
- We now support all multiples of 8-bit data widths even for x16 memory devices.
5 s9 e4 n5 P1 H h, s0 S- We support memory devices of speed grades -3 and -667. 0 O$ O" l, e0 Y
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. " ^: Z$ z: r( t! V2 U( m
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
3 s7 a' u, c7 `7 }b. WASSO is applied to all the memory interface signals. $ ?' P! K- o5 Q& ]3 I
c. Signals such as "Error" outputs are not part of the WASSO count.
+ Q2 r) m. P6 L' `4 p
3 K+ Y2 v. e1 L' K$ }4 \8 DDDR2 SDRAM SERDES Clocking 2 a( u% `) f9 p, ~' W
- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. * \- {* T' Z0 W8 I
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 4 l L p/ A7 L7 x2 D1 n4 m
- Support for ODT.
/ Q! r0 j! T2 o" m0 S- X- DQS# Enable is selectable from GUI through Mode registers. 5 J ~- P5 W- ]$ G# d9 `- ]
- Removed all TIGs in UCF. The reset signal is now registered in every module. 7 G" I6 j/ j/ z0 g# m1 {+ l: l! A
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
. p" z) C( a8 g, n- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
0 Z, u" I' B1 ]( ?* ]- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. : w. e: v6 |' }4 R
- Replaced `defines with localparams for Verilog. 7 N7 M9 v# B! `* X& c9 y
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
6 }" @- o, H p0 @ [- Removed the UniSim primitive components declaration from VHDL modules. / ^+ _! b% O" _+ d. j$ |
- We now support all multiples of 8-bit data widths even for x16 memory devices.
' Z! `& O* k) H3 X- Signal INIT_COMPLETE is brought to top module.
' } g0 l3 ]6 {/ {# M* e- Memory devices of speed grades -5E and -40E are now supported.
6 K2 R% [* K8 D7 W) @7 p( | ~& F, t* p/ M- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
: |( @7 ?* L. w" ^- Z7 Da. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
6 b9 E! X! B1 J3 j5 nb. WASSO is applied to all the memory interface signals. : [9 `! f+ s& a l! n
c. Signals such as "Error" outputs are not part of the WASSO count. & Z. o( \/ I+ ^
( s: ?5 e# o% U. uDDR SDRAM 2 k; {3 m; ], n' i- O
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
! R2 f; ]7 t8 p2 \* S' q6 q8 {8 n- Removed all TIGs in UCF. The reset signal is now registered in every module.
5 _* n# Y7 s% V! F6 e( r! E6 {- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 7 e' Y% \3 z0 Y$ v/ {
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
# b4 t0 e/ i, B! n6 w- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
w: Y2 `: w% J- Replaced `defines with localparams for Verilog. $ [' p* M; i3 e" z: N
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
! u) u# W* f7 c+ A0 ^) X- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
' d& k9 f5 v# [2 ]7 d- Removed the UniSim primitive components declaration from VHDL modules.
2 I+ c1 G8 p! F- We now support all multiples of 8-bit data widths even for x16 memory devices. 8 H' Y, l( r2 q- B. {: U
- The signal "init_done" is now a port in the top module.
! ~" L6 A& K1 M M- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
1 e/ x& t/ V3 S, Da. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 4 E: E E8 n0 f+ M/ F( P
b. WASSO is applied to all the memory interface signals. $ w/ ` m" }3 s
c. Signals such as "Error" outputs are not part of the WASSO count.
- E" e- X! M+ p5 |6 [# @: n0 Y1 w; i4 b
RLDRAM II
% W) R2 w! D& \1 ]1 x6 l4 U- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
0 k8 h9 f0 [" o- w4 x7 @9 b- Removed all TIGs in UCF. The reset signal is now registered in every module.
+ q2 C2 t' M' A- The design now uses CLK0, instead of CLK50 and div16clk. - s1 W: k' D3 X- I9 x$ Z" R
- CLK200 is changed to differential clocks in mem_interface_top module (Design top). ) Y! J/ ?2 R0 T/ Z+ S6 Q$ V
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. 5 o/ L! D( S/ g6 Y" E, o
- Removed unused parameters from the parameter file. 4 Q5 ?; x) l$ }5 y' E! o0 a
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- b+ ]( A& ]3 e7 n- M- Replaced `defines with localparams for Verilog. 8 m; y6 a. Q& G
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
6 [5 ^7 A9 U& K9 ]& n! P' t- Removed the UniSim primitive components declaration from VHDL modules.
% Z: A W+ g, N% d- The signal "INIT_DONE" is now a port in the top module.
8 O; I2 h. y9 E" |/ W) l/ O% z- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. 6 z$ _" G; @5 a6 B9 f2 h
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. 7 P H0 i5 G( a* R6 V B: \7 h
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
- Y/ ^+ \2 V3 c. Z( q- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 0 B, _% Z% P* F$ S6 o( l+ f
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ! A; u3 H* v! T# h6 y
b. WASSO count is applied on output signals only for SIO memory types.
; @$ i1 c; Z2 _c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. i. i% W& L& p: m7 j0 {
. z1 `. W A5 O0 N
QDRII SRAM , d7 R( _" n1 I$ \( T
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 0 ]) L) A. H9 L. H$ n6 T" b
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.
/ g. C* T5 e: Z. _- Supports generation of designs with out DCM.
& b; w5 Z5 |# |0 c3 S2 g- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. 3 n, g! W0 A. _, ^& r* ^
- Removed all TIGs in UCF. The reset signal is now registered in every module. * x+ r+ ~0 f: F, \" i# G* I$ j
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
/ Z* H" `& @& l6 `1 d: W) |+ L- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. & T% j& k# n- D# N
- Replaced `defines with localparams for Verilog.
* q. C. i/ y3 O3 s( I- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. . i8 u0 I" Q. j9 G% m5 B! P
- Removed the UniSim primitive components declaration from VHDL modules.
9 t& [ Q# n; T" |9 g- The signal "DLY_CAL_DONE" is now a port in the top module. * }0 O1 W0 ?. D: X a: M9 y
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
7 k# D; e& e4 ~8 O3 G& `- Added support for DDR Byte writes. ; s( U+ B% c7 q8 N1 H
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
' H7 B3 B3 I" b# fa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 7 w3 a1 j m" ?, H
b. WASSO is applied to the output signals only.
4 K2 G' [( k" I' [" hc. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. . h$ N( K) U7 S4 N4 Z; X' ]5 _9 i
+ U ?6 f) M% G6 M/ L9 v. WDDRII SRAM
3 W/ ?# F c8 q* x- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
: M; H7 B, x, O5 m% u- a+ q- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. 0 A2 G: l! H$ A1 v" o
- Supports generation of designs with out DCM. ; f Q8 v8 o' D2 l" B
- Part CY7C1526V18-250BZC has been removed from Memory Parts list. ( R! h5 c1 Z- b$ d
- Removed all TIGs in UCF. The reset signal is now registered in every module. " Z+ j! c' [7 q$ @4 E
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
. P: }0 b$ @ j/ U8 `- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 8 s, q. E' q" p! H/ E
- Replaced `defines with localparams for Verilog. " O; X8 [5 H7 ~7 L& b$ I. i
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. , s- i# @$ r8 z9 r
- Removed the UniSim primitive components declaration from VHDL modules.
! s# T0 B4 i( G5 ^8 \7 r- The signal "DLY_CAL_DONE" is now a port in the top module. , N0 ?! K1 j1 ]. L9 Q: P
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
8 a, X; r+ i+ u# ^/ c) r0 ]2 Z, [- Added support for DDR Byte writes. & ?$ i, a7 D x/ K9 v- y
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. / R9 Y4 D$ d( J1 K, f( b* V* B. }
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 2 W5 `3 Z4 y5 ^$ b
b. WASSO is applied to all the memory interface signals.
- o8 `) d5 M4 P9 hc. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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