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回復 #1 tom218 的帖子
問題不夠清楚哦?????要VHDL還是Verilog??? 8bit的count有很多種,要up count還是down count?????要有加reset還是....????) X4 ~) f9 o. O# k3 B3 n+ g
我給你幾個參考.7 B4 r7 n4 S3 @+ B
/ G8 Q ?* x# p: c" SVHDL count' g/ q5 `* j8 |4 B, R
+ r# c" f1 R E! Y
process (clock, reset) 1 F! {3 i9 j) }5 d" j) C. Z
begin) a' a+ G" p2 N5 ]
if reset='1' then
$ B% x1 i- m, B7 z! c count <= (others => '0');
]6 n+ U$ P: H& u! a, t elsif clock='1' and clock'event then. ]- Z- p T- k: R0 I2 I+ ^, I" |- u
if clock_enable='1' then
6 B5 }$ U. }+ S" C9 o2 X" _0 e count <= count + 1;6 W* P7 o; {" Z
end if;
7 ~$ E+ `: F: C5 R end if;
' e i2 ^2 ^0 |end process;8 s! w( [3 f6 }3 q% q! x
$ x, V8 _: Q$ O( J
Verilog count
) x$ ?# ~/ t; i: h$ w/ d$ |+ y% G6 u1 B" { c2 \" _
reg [7:0] count;
* t( ]- `, v( c) k0 E, U
3 I$ \2 j0 P3 j always @(posedge clk)
) ~" V: f- e! c8 D" o6 F, T: o if (clock_enable)4 F- m4 k! V3 o5 L
count <= count + 1;& s2 ~7 i% Q- g; |# p5 `% ?
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VHDL比較器* Z' O& T9 l9 w
process(clock)
& ?- i# l5 y. Fbegin# Y; K4 y( B. F4 X' x/ f4 a
if (clock'event and clock ='1') then
% W! f: r- [( t0 R/ Y% ~$ P if ( input1 > input2 ) then
4 S7 k9 `8 |/ g) p* I9 p0 i output <= '1';4 t; B; c% ~+ C8 L9 s
else
! M9 I+ Z! N! t& J7 u/ K% t, | output <= '0';" p, Z5 f/ V$ ~0 @/ A
end if;
$ ~* B# x" ^; c! Y. _ end if; % c+ I% d1 \$ M& M* t! O9 W+ }' N6 O
end process;
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0 j& h) a3 O7 Q4 Y7 g% Y; Nprocess(clock)# F* Q9 |7 {. [3 M8 g
begin
" L. Z- |0 p) X% S9 s- g1 i% A if (clock'event and clock ='1') then
8 J: ?0 y% z3 m& U if ( input1 < input2 ) then . I c- U/ B. ~. g- m
output <= '1'; J) s! F( \4 d& B2 F H- m
else
+ g' {5 D4 ~3 r! ` output <= '0';
7 m1 P, `: ^; K3 ]+ p& R end if;
7 S0 o* j! K8 y0 Q end if;
% ^4 x$ `- a2 V7 i) Fend process; 7 d* i; h2 P n8 B# M
* ^: W6 {. A1 i7 u7 R0 n) d, QVerilog比較器
, ]# e1 l. h. Xreg output;
: F4 J7 g7 @! e& R( z; m; N" ~
; |' u% Q' z. H }( m6 Q$ n) q always @(posedge clock)
0 D1 j8 q% I; z/ |5 X. e if (input1 > input2)
9 i* ?# q6 {3 [& M output <= 1'b1;
2 `- G* |- v4 ?$ [' c6 b& F. u else
- E9 s# E# N( e0 e1 ? output <= 1'b0;( G* j; v2 D [- o
% @7 h+ E: g) s7 O
reg output;
8 P* b |) ]+ _1 S3 d4 g: S& [& o- s7 Q( l: ~) b" a
always @(posedge clock)2 F0 z' a! E5 s
if (input1 < input2)
! O1 x* D S: N' ]& q output <= 1'b1;2 ?0 _% |# c" X' V
else {7 H# E* k: ?3 P' y4 A6 r' T
output <= 1'b0;
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希望有幫助^_^ |
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