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剛剛找到嚕
: d$ _* d0 `% k3 ?在這裡
$ k$ p$ X+ g D/ S5 V xPrimeCell Fabric IP
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PrimeCell Peripherals
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, ^# T; f8 V* {( [6 i. B0 ]& |ARM PrimeCell Peripherals are re-usable Intellectual Property (IP) macrocells developed to enable the rapid assembly of System-on-Chip designs. Ready to use, fully verified and compliant with the AMBA on chip bus standards, the ARM PrimeCell range is designed to provide right first time functionality, high system performance and best value IP to designers.
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: i7 l3 }! p FUsing the ARM PrimeCell Peripheral range can help you to save considerable development time and cost by concentrating your resources on developing the complete solution rather than designing generic functionality devices. ARM PrimeCell Peripherals provide designers with a library of proven functionality that works reliably, and affordably, "Out Of The Box"., z' T+ \1 @" x+ D# c3 m, g
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Overview' D. M% e6 b9 U* V% w8 Z1 F# z
# S9 [. C) R$ j3 K1 KHighest quality ready to use soft IP macrocells( _6 N3 x) B+ m2 v
Industry standard AMBA compliant
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Proven in existing System applications , z" P1 ?# y2 D, {6 i
Developed to strict design guidelines ensuring easy integration & reuse
; e/ A( n& F4 w+ O4 M, BExtensive & detailed documentation , X7 J; S6 m/ a' x
Comprehensive support network
" e- `' V$ Y7 ?. Z, C3 Z7 [2 O/ o( nCompatible with industry standard tool flows 2 u0 S v8 `4 Q" h3 e1 x1 d- \
Evaluations & full licences available today
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PrimeCell Peripherals cover the full set of AMBA standards and their functionality targets a broad range of purposes from very high performance through to simple I/O. For example: u; Y8 C+ h4 r, m
* D% q7 t5 ^+ W. H3 ?; ^' N+ oInterconnect Generation 8 V4 ~+ i1 `. ~0 }
Memory Controllers
/ Q% c% I, B# B, f ?DMA Controllers 6 _ Y# U- j3 T' G' K* _9 V, X
Level-2 Cache Controllers
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Interrupt Controllers
- l" n- g% c' c. a0 C' BGPIO's & UART's
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! ~ c/ c1 `3 U% \% R9 N[ 本帖最後由 masonchung 於 2007-5-13 11:37 AM 編輯 ] |
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