PLL 的實現方法?

tieyuhsun

//可直接透過synthesis  tool用於PLD，FPGA不可 LUT delay則要採其他方式。
//所有註解都要保留
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- m! i6 Z; F: p% y6 [: f( W- t`timescale 1 ns / 1 ns
module xclk(sclk,ena,set,outp);
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input sclk,ena;
* H, q( w) s; linput [1:0]set;
output outp;
  u( F4 B+ X( s; y
wire outp;



; |9 r% G1 g) b* Z8 G/**** Node preservation for nodeA **************/
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' \  v) @$ g$ ?$ O9 t  x//exemplar attribute nodeA_5 preserve_signal true

  |; M5 O% c8 K9 @* ^* w//exemplar attribute nodeA_4 opt keep
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/**** The following comment form also works ****/

//exemplar attribute nodeA_3 preserve_signal true

4 B/ N, M! Z' M1 p8 T7 `7 D* O//exemplar attribute nodeA_3 opt keep

/**** The following comment form also works ****/
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//exemplar attribute nodeA_2 preserve_signal true
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0 G+ Y4 W' Y0 z5 W' Y# [//exemplar attribute nodeA_2 opt keep
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1 a9 `, ~' P+ x5 n  J9 H3 B" a+ W5 P+ ~/**** The following comment form also works ****/
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//exemplar attribute nodeA_1 preserve_signal true
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: Z' \; o4 [  q7 A- ^. l6 z$ q//exemplar attribute nodeA_1 opt keep


. t# s: g, p5 l. i1 H6 x/**** The following comment form also works ****/

/*exemplar attribute nodeA_0 preserve_signal true

exemplar attribute nodeA_0 opt keep*/
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wire nodeA/* synthesis syn_keep=1 opt="keep"*/;
) A3 m# z  o& o# p3 fwire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
; y4 i3 F' C3 ]9 T9 x1 c! d3 Gwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
7 a% P8 m* d$ nwire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
wire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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4 Y4 M) w- E5 P+ E& i" N1 S9 Q( vassign#1 nodeA_0  = sclk & ena;
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assign#1 nodeA_1 = ~ nodeA_0;
assign#1 nodeA_2 = ~ nodeA_1;
assign#1 nodeA_3 = ~ nodeA_2;
assign#1 nodeA_4 = ~ nodeA_3;
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$ u& W, F/ T% ?, Greg xout;

always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
  casez(set)
    1: xout =#1 nodeA_2;
5 q8 ]' T$ _' Y) C8 G! v( ~    2: xout =#1 nodeA_3;
    3: xout =#1 nodeA_4;
" x# }7 i0 h; f$ W) ]. b1 ]% R    default: xout =#1 nodeA_1;
4 e; m7 f, o" k) K  endcase
  
( g; e8 Q& O. k6 hassign#1 nodeA = xout;
assign#1 outp = ena ? nodeA^sclk : 1'bz;

endmodule

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" G2 @) ?9 B" `( L1 o, U* E`timescale 1 ns / 1 ns
module xclk_tf();

5 j5 V) ^  o& s0 `# G// Inputs
    reg sclk;
( s7 E: L; N/ _1 a1 k    reg ena;
( r' K) y9 |) a* T7 L% [    reg [1:0] set;


" D% T1 E. b! p  F6 S2 z// Outputs
4 O0 J% C6 t& T5 p    wire outp;

. E2 W! g0 y# X: i- u# }) X

; `2 k. {! s+ T    xclk UUT (
        .sclk(sclk),
        .ena(ena),
        .set(set),
8 T8 {& \6 Y+ x# }% X1 G2 X6 G        .outp(outp)
5 N  R: ~" s3 W        );
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- S. z% J; F- x. \    initial begin
" h5 a$ v7 k: D# E! V            sclk = 0;
            ena = 0;
/ [0 n7 G$ g9 l- M* h: Q% n5 C            set = 0;
    end
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always# 5 sclk = !sclk;
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initial begin
9 Q1 I. ]) C- R7 L        #100
          ena = 1;
( W7 P/ S. R/ G9 b7 V: h        #2000
- }6 m8 K4 i* y7 ]          set = 2;
        #2000
% E' T5 @# L; d          set = 3;
  #2000
& {* Z( c# J  z  $finish;
end
endmodule // xclk_tf

tieyuhsun

有附 test bench
9 j( l3 |# A; S# W確實可用！ 已實驗過，但我不會貼圖。
只要略加修改即可實現。