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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
1 x7 o( g1 e0 H//所有註解都要保留* H# n1 ^+ ?/ ?% `5 L
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`timescale 1 ns / 1 ns
; r7 g2 a3 L) P% ~module xclk(sclk,ena,set,outp);
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$ r+ W9 l& |0 x3 ^" ^! u ~$ dinput sclk,ena;8 }$ H7 {( y5 s7 i8 ]/ ~$ ^7 ~
input [1:0]set;
3 o0 c, y* L" E+ \output outp; 5 B5 ~# S5 J/ \
0 F5 P& f) U E5 b5 ?, g" }" Q( c+ jwire outp;
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/**** Node preservation for nodeA **************/) Q! F! ^- } w" V- R
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( h5 u9 } M, H//exemplar attribute nodeA_5 preserve_signal true; \9 Q4 K" C' M" a8 E
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//exemplar attribute nodeA_4 opt keep' `! L. q/ _9 G F2 W
* q) r/ O. K) l& ~$ r6 i' |* V/**** The following comment form also works ****/6 i! @. I4 C0 c- e4 j+ a
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//exemplar attribute nodeA_3 preserve_signal true
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//exemplar attribute nodeA_3 opt keep, Y, }- D9 O# g, v6 r
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_2 preserve_signal true
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//exemplar attribute nodeA_2 opt keep0 H6 I! }$ K# P( h* R3 d7 F
; A! H9 l: J& @& `. [8 J+ W& E/**** The following comment form also works ****/: s5 R" v7 r0 A# U- I7 G' y
' X, _9 X F) {5 ]//exemplar attribute nodeA_1 preserve_signal true& L0 \" K3 g) ^/ i' r
# f' f9 `( F2 t4 y- |: D/ G) ^//exemplar attribute nodeA_1 opt keep
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1 l2 L0 p5 }3 K. s/**** The following comment form also works ****/
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/*exemplar attribute nodeA_0 preserve_signal true& D4 Q# m( S9 J& M: _6 M# E; R
8 W0 D) I2 u% e8 K* G) S& o, qexemplar attribute nodeA_0 opt keep*/ 7 L n" p2 e: h7 m
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6 ~! X+ R! d( P, Q! ]wire nodeA/* synthesis syn_keep=1 opt="keep"*/;1 E4 a; _; b; B
wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;- t( Y- l% H# H
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;# z+ y8 G- I# o! r" ^4 R% X
wire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
1 S& ]/ X7 F9 [wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
; P& L9 }+ \ Jwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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assign#1 nodeA_0 = sclk & ena;8 g+ V- M/ }# y3 J! s; @
1 z9 ]. `+ C: I# cassign#1 nodeA_1 = ~ nodeA_0;
: |. Y3 Y2 v# b: J. I5 Jassign#1 nodeA_2 = ~ nodeA_1;
3 v5 R' @# Y4 A% \% v& ?* a/ z" uassign#1 nodeA_3 = ~ nodeA_2;
: B- s$ w( A" h+ _assign#1 nodeA_4 = ~ nodeA_3;" n2 I% g' c! ]9 @/ {/ }
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reg xout;
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
3 V- l6 F! T1 B) g, U1 N casez(set)
& Y3 h, ?5 L$ S5 y 1: xout =#1 nodeA_2;
+ i. U+ N) p1 } 2: xout =#1 nodeA_3;
5 }6 V! ` M% _, z2 l! a# t 3: xout =#1 nodeA_4;
* Y8 |0 n) P# ^ default: xout =#1 nodeA_1;) ]1 P, z9 e0 Z4 E. g) x
endcase9 }1 p r. o/ ]4 C% C: W- L" l8 Z" E
9 p9 O1 D$ n0 ] h$ Fassign#1 nodeA = xout;5 F& Z+ \6 w/ W; X" y) ?, E
assign#1 outp = ena ? nodeA^sclk : 1'bz;
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! Z8 \; [' k W`timescale 1 ns / 1 ns
' k8 f9 |/ E$ g3 Xmodule xclk_tf();8 E% Z- I3 O' z1 r4 Q" g
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// Inputs
9 |* U, K+ b% Z; l" f7 M d3 g reg sclk;
( V3 Z4 [4 m( M, \4 h* V0 I! @ reg ena;
! X- C# d, {4 ^9 Z reg [1:0] set;3 y* ?& L. J: I* i, j0 S
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/ }, r9 f. W8 f& h! W/ E// Outputs
# j! R0 g$ U) }3 e. k' B wire outp;# H/ ^" z0 j& Q; C
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xclk UUT (; a+ e4 E- U4 ^" t, V: C7 N/ E1 Z
.sclk(sclk),
' k8 y( O, D. ]2 p3 y# V0 q .ena(ena),
, @3 `9 U/ \6 K8 \: Y .set(set), 8 k! W9 q1 B, I3 O6 C* \ f1 b
.outp(outp)
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7 ?1 @, p! v }7 D6 Q1 |0 s- c% W" ?3 H initial begin: i# U0 m0 ~% ]" I5 G# G5 s
sclk = 0;
2 b! }4 k9 O3 m& I9 z+ M; J% a. \ ena = 0;) K( G5 t: K& l/ S; q; x8 z0 a
set = 0;# Y- |0 o2 j# M3 Z% d
end+ W8 M2 i9 }1 R' q3 a
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always# 5 sclk = !sclk;% h( R9 T5 B7 \' A
1 t: u$ G: H* J- O0 V) T) G' Winitial begin
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ena = 1;4 w7 k% g4 }5 P# L, ^
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set = 2;/ L+ \& S( M6 @" R* W
#2000
# N. _0 W- k* q: k( X4 x" r, h- @5 q set = 3;3 M6 v; m5 f3 A- F- @
#20008 H# F. b' w3 C o% Y, a! Z0 ]+ K$ p
$finish;
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endmodule // xclk_tf |
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