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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
! V7 D F( U c" h5 l//所有註解都要保留: b Y+ G0 H V9 w! l* P
% T. M! a( R7 X/ [% o2 I`timescale 1 ns / 1 ns0 y Z$ V- T4 {; J
module xclk(sclk,ena,set,outp);
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input sclk,ena;
5 x- r$ y* ]8 d8 \+ \0 v8 X8 T5 \. [; Ginput [1:0]set;
* y4 M4 O1 w$ S- \$ [) Houtput outp; 4 Z! E( D1 D* O* p
P, X% T1 {3 d7 Gwire outp;
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# @2 s5 |8 ^6 e, ~! U' W/**** Node preservation for nodeA **************/+ P) \0 F! T Q4 h
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# ~0 Z6 |4 g' a5 ^//exemplar attribute nodeA_5 preserve_signal true: L! U) a# x! j7 \& s# X2 m+ v8 e, \$ C# S
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//exemplar attribute nodeA_4 opt keep
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1 }9 G* D& A1 r0 Z3 ]# x8 y/**** The following comment form also works ****/
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//exemplar attribute nodeA_3 preserve_signal true. e+ \ r+ I9 b, G/ v
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//exemplar attribute nodeA_3 opt keep
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; A3 j8 x4 B% T7 d. m. W# H/**** The following comment form also works ****/6 J# Y" }" z, j/ H0 H* E
1 e( @( J: d5 R7 o: C//exemplar attribute nodeA_2 preserve_signal true; N- z/ t. h7 s+ g, [& c
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//exemplar attribute nodeA_2 opt keep7 |* E1 i# `- K3 z- E# d5 \
. x7 l6 P' H* e% H) S, J" P" ?2 r# E/**** The following comment form also works ****/
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* ]/ {/ a8 l* O- T1 A( ]* M+ X//exemplar attribute nodeA_1 preserve_signal true* p2 W, y0 j4 {3 l( i; m' [
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//exemplar attribute nodeA_1 opt keep; T8 c: Y9 J, a' K' c8 s! M" ^) v
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/**** The following comment form also works ****/: u J3 T9 G x( f; @1 F
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/*exemplar attribute nodeA_0 preserve_signal true* L( u5 D/ g5 G2 `' A
1 C8 D9 f. }! B& @: [" R6 A: yexemplar attribute nodeA_0 opt keep*/
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4 K5 g* n {! }8 `5 dwire nodeA/* synthesis syn_keep=1 opt="keep"*/;
* p) D- ?- ^+ G8 Xwire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;
+ G" o# ^8 U1 uwire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
! B* F6 Q1 V) h3 r& t$ B: J+ jwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;, T, }( v# @) W9 |3 d% d; f
wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
9 P; ]( w! {& swire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;* X, q+ F e6 s' a9 I. e [
$ Q& L( N _& [( C$ R* }8 z, Nassign#1 nodeA_0 = sclk & ena;" t. v3 E: r: T
( a, @$ \" ^: J; q; d, q, ^) Vassign#1 nodeA_1 = ~ nodeA_0;
6 i/ |+ K2 w1 F6 m2 Aassign#1 nodeA_2 = ~ nodeA_1;+ ] u- C8 `& [; u" Q
assign#1 nodeA_3 = ~ nodeA_2;
`$ }" w! w! xassign#1 nodeA_4 = ~ nodeA_3;9 G4 P) l' i M
. M1 K% U: {6 _0 C" _reg xout;
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
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) e4 U5 {& \0 H9 m9 M- s/ M 1: xout =#1 nodeA_2;
2 S5 {3 `2 ]7 U) ? m& ~ 2: xout =#1 nodeA_3;
8 H8 b; Q- H5 n& h2 ^0 ]$ d6 g 3: xout =#1 nodeA_4;
0 x! J# h: K9 b4 Y5 _$ A- L default: xout =#1 nodeA_1;
) h2 F- z4 |! K3 T endcase3 z* O3 _4 P) Z0 W, g8 c, I0 b
( e: }1 N$ S; }# C) X# H& m5 Qassign#1 nodeA = xout;
3 d; G, }1 P( F6 x3 z% V8 C' a7 lassign#1 outp = ena ? nodeA^sclk : 1'bz;- B( u* {6 \) t% J& I, R
+ v1 N) T8 S4 Iendmodule4 e0 X5 A! Q, E) h
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5 t& H- ]+ g, f' ~: W( Y, G e: ^`timescale 1 ns / 1 ns" H5 Y0 \- a p: X) x, {2 U
module xclk_tf();
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n6 k0 A4 E- n. G; w// Inputs1 ~) x0 M$ m/ m2 K; n' k
reg sclk;
% v, @( M* E, v8 P; k reg ena;
) r6 B4 @$ t' A/ G" B* y# A, B4 O reg [1:0] set;. R q; G, r2 c+ U& m' E
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# L K. Z6 B" y% n# D) p// Outputs# `9 @6 f/ l# w9 g7 ? C
wire outp;
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xclk UUT (, M! T5 A# ]! B5 m+ g5 v
.sclk(sclk),
/ B% n. Q5 r. y' r .ena(ena),
/ ` ?: f2 O' w1 N) W$ y' B+ G3 Y .set(set), ( q6 w- j6 _4 D( [
.outp(outp)$ T7 s4 X, |- X" t
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6 g; B9 N& U6 i3 ^% U, Y initial begin7 |# T! [9 I- z# D
sclk = 0;
% i% U n' L5 V$ d) S! u' V) g& E ena = 0;) C2 ^' L/ S. ~9 D+ n5 A
set = 0;
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7 O; C! D: B) ]9 g! Calways# 5 sclk = !sclk;
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initial begin9 P) I; ], ^/ T
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ena = 1;
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( D! t. g# \/ {2 D1 r$ q #2000
4 u! K: J: C5 D. h4 I% r set = 3;% W8 z1 t* A! C4 b& h# ]* z* E: T
#2000" m/ K0 r! N, W: L" g* P) A
$finish;) F, C3 r+ Q; ] n$ Y* O9 M5 ~
end6 z8 s6 I% c" P+ a4 `. A
endmodule // xclk_tf |
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