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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
$ t6 S, D5 S, K2 u" ]7 i//所有註解都要保留
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1 a- R4 G, \/ V! | \' j1 G9 Q! ^`timescale 1 ns / 1 ns
0 u3 ?; W, t% s. [* K. j: q1 cmodule xclk(sclk,ena,set,outp);
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input sclk,ena;( \; p! G: p! p& ~4 G
input [1:0]set;
) m: M+ \# C) ^9 d" w% _, _" I! loutput outp;
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wire outp;- {+ s( ^9 o* m7 x5 t* @$ {
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: g) G! l- w3 u s/**** Node preservation for nodeA **************/
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0 J# F- h( ?; `% A6 |2 P4 w! D! p//exemplar attribute nodeA_5 preserve_signal true' A7 G3 F8 f+ r$ b- H
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//exemplar attribute nodeA_4 opt keep
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/**** The following comment form also works ****/
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, x* n. t% L1 C9 I, }3 y) w3 h//exemplar attribute nodeA_3 preserve_signal true( M+ l: U& S, }# X% S
* [9 w8 W/ ]/ o; O//exemplar attribute nodeA_3 opt keep
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! _/ z5 G2 M7 C p4 _2 K/**** The following comment form also works ****/
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; \. W) v1 d1 C) s% ?4 A/ P5 t+ ^//exemplar attribute nodeA_2 preserve_signal true2 S! i4 [5 R7 o9 S8 b. O9 d
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//exemplar attribute nodeA_2 opt keep
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_1 preserve_signal true+ f! P# Q% J/ T7 i% Q& k
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//exemplar attribute nodeA_1 opt keep5 r! z7 [2 F5 G2 p C! D0 a0 h# c
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, ^! I0 `! w: }/**** The following comment form also works ****/$ g6 _9 s0 L; r* e6 ~% e$ X
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/*exemplar attribute nodeA_0 preserve_signal true7 ~! Q& j* ?8 Q6 t, @
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exemplar attribute nodeA_0 opt keep*/
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' j& ], d$ o* G3 R7 Owire nodeA/* synthesis syn_keep=1 opt="keep"*/;
5 V+ x, L! U) c! p6 R4 ?8 Ewire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;7 ?3 ^& p" i$ `( m) \
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
L! y8 f( A0 s6 Bwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
7 J- z7 j! \5 r' T$ `- cwire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
; M: R. [% ^' n- K) l: P9 ^, Dwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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8 C* w' ]) u% N: g: Sassign#1 nodeA_0 = sclk & ena;
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assign#1 nodeA_1 = ~ nodeA_0;
; W# {' r0 G) b, N+ v2 ~% D Yassign#1 nodeA_2 = ~ nodeA_1;
. i" P: j7 J* O( C! A) N- oassign#1 nodeA_3 = ~ nodeA_2;4 b& e2 [0 f- @- t- o5 N! U
assign#1 nodeA_4 = ~ nodeA_3;
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reg xout;
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)2 i6 h. j, |3 ] ]$ y2 g
casez(set)
2 v9 x( X; z( f3 h9 e 1: xout =#1 nodeA_2;
; z2 w) S* d3 L& Y 2: xout =#1 nodeA_3;
5 Z$ M2 r* R$ i- f% { U 3: xout =#1 nodeA_4;
) ^# R s3 y- {2 p# W default: xout =#1 nodeA_1;
9 ?& k5 e; Q8 t } endcase% J0 x+ A: Q" O9 C
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assign#1 nodeA = xout;
( Q% A" Y& w& a: B$ R$ s& |assign#1 outp = ena ? nodeA^sclk : 1'bz;
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( F8 e' H- R8 V( I: {9 R" f, Aendmodule
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- S" J8 [/ T7 O1 ~( |: G`timescale 1 ns / 1 ns* W+ {* K! i) ?; j: s$ e
module xclk_tf();" P3 a' s3 n3 R8 f5 K. K
Q% O" J) W: H9 z! {// Inputs" h- t1 S) w- [ T: A/ f
reg sclk;9 w. u# f+ |" B1 ^: I. s
reg ena;
# l1 B5 c1 l% K' N reg [1:0] set;
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/ {8 N( U7 a4 E1 a. q9 |5 [// Outputs
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. S1 y8 Y0 {( k, ]5 K% B xclk UUT (
& v3 m( ], q" X+ S0 R3 E .sclk(sclk),
' {( D8 A1 w2 \' z/ U .ena(ena),
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.outp(outp)
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. u$ `0 Z. K/ q9 B initial begin
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ena = 0;
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end/ S2 ^+ {6 J' B8 l5 N! j" E3 m- N
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always# 5 sclk = !sclk; x6 l, \1 g7 F" }
: o& \! c$ \+ b/ T: y yinitial begin
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ena = 1;; s' f( `: n2 s0 o# X# d6 k& |
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set = 2;& w2 j, W/ B" z% H7 n' g0 K
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set = 3;7 l9 |3 j, u) x5 L2 L; H* K1 `
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$finish;
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endmodule // xclk_tf |
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