The Xbox 360 CPU architecture

masonchung

The Xbox 360 CPU architecture

5 }7 w. _1 l' {4 X) p- G  LThe Xbox 360 system has a single chip (with 165 million transistors) for its CPU. This chip is in fact a three-way symmetric multiprocessor design. The three PowerPC cores are identical, except that they are physically reflected through the X and Y axis. Each of the CPU cores is a specialized PowerPC chip with a VMX128 extension related to (and partially compatible with) the VMX instructions in the G4 and G5 CPUs. The three CPU cores share a 1MB Level2 cache. Each processor has 32KB each of data and instruction Level1 cache. The chip's front-side bus/physical interface has a 21.6GB/second bandwidth, and runs at 5.4GHz. The high frequency clocks are generated on-chip by four phase-locked loops: two for the core clocks, two for the PHY clock.

& a7 Z7 `9 D4 l+ bThe Xbox 360 CPU chip has testing and debug functions, including tracing, configuration control, and performance monitoring features. Access to these functions is through the block in Figure 1 labeled test/debug. The block labeled Miscellaneous IO provides a JTAG port, a POST monitor, and an interface for a serial EEPROM in case patch logic configuration was needed during bring-up.

To improve manufacturing yield, the SRAM Arrays used in the L1 and L2 caches support both row and column redundancy. This redundancy is enabled at chip test by burning electronic fuses. The eFuses are one of the unique capabilities of the IBM 90nm CMOS SOI technology the chip is fabricated in. Efuses were also used to record a unique supply voltage to be used for each chip. Finally, to help reduce the potential impact of process variations on the operation of the PHY analog circuits, eFuses were used for parametric adjustment in the analog units.
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The physical package of the chip matters, too. A crucial design goal in the CPU of a consumer electronics device is high volume with good yield and comparatively low cost. The package is a 2-2-2 FC-PBGA, measuring 31mm by 31mm.
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The CPU core examined
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The CPU cores (there are three) are the highest frequency PowerPC cores currently available, running at 3.2GHz. Throughout, the CPU uses extensive clock gating, leaving pipelines shut down until there are instructions to be processed; this dramatically reduces power consumption under real-world loads. The basic design is a 64-bit PowerPC architecture, with the complete PowerPC ISA available.

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The instruction unit is multithreaded, with two simultaneous threads. The instruction cache is 32KB. The core implements a two-issue, in-order execution microarchitecture. This means two instructions are issued at a time but execution within the units is in sequential order. Execution is delayed to cover the load use penalty without stalling the pipeline.
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+ U9 z3 G8 L% R) Z2 p; W, YThe L1 instruction cache (Icache) is a 32K Byte cache with parity error checking. It is two-way set associative cache with 128B lines. First-level translation for instruction addresses is done using a 64-entry, two-way set associative effective to real address translation cache.
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% ^& T1 J$ a+ `2 \1 {The two issued instructions can go to one of five execution pipes: Branch (which is really part of the instruction unit), Load/Store , Fixed Point, Floating Point, and VMX. Difficult instructions are implemented through microcode. At dispatch they are cracked and converted into multiple micro-ops.

The branch unit includes a 4KB two-way set-associative Branch History Table per thread.

# j/ m) f& [4 y9 VThe Fixed Point pipe actually has two units: one to handle the simple operations like (add/sub, cmp, logical ops, and rotate); and one to handle the complex operations like multiply/divide.

$ r% A! _1 e$ J7 w( fThe Load/Store pipe handles access to the L1 Data cache and the storage hierarchy. Like the L1 Icache, the L1 Dcache is a 32KByte cache with parity error checking. However, it is four-way set associative. It is "store through" and provides non-blocking access so a cache miss does not hold up a subsequent hit.

A 64 entry two-way associative ERAT handles first-level data address translation. Second-level translation for both data and instructions is handled by a 1K entry four-way associative TLB (translation lookaside buffer) which can be software as well as hardware-managed.
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8 f5 M/ J* \/ }4 m. z7 D0 Ghttp://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign
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[ 本帖最後由 masonchung 於 2007-2-9 10:41 AM 編輯 ]

armmips

感謝分享，這是很有用的資料。
8 j3 s1 D$ r* t3 q) W5 p& M5 J只是3+1式的多處理器架構，會不會有編程上的困難？