|
Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks& _ i$ C6 q% E1 o8 N& E$ |- e( ~
然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack - Q& \3 d, k2 a) v- W) q
之後卻有如下之 Meaasge:
2 F/ ]7 r. @) h' v
" y) |/ u& K# n; s******** Pin Access Analysis *******
' j) P7 ]6 ^3 O$ X** # Cell Masters = 1000$ X3 G8 F; M* }0 U1 b. O* N- w8 v
** # Ports (logical) = 2500" G/ D! Z- ]6 X3 |
** # Pins (physical) = 2500
( a3 r) p1 D( }, q7 t5 W* {& @6 w** # Pins with no good access point on Grid (V&H) = 5 ( 0%)
+ v/ I8 }! x- d0 [, ^" q** # Pins with no good access point on Ver-Grid = 5 ( 0%)
5 \" @- B; L6 i% @' K: S9 y/ \* e) t8 [! b d- p p
請問下面這兩句是代表什麼意思呢?" {( t3 p7 @. ?2 j. P+ o
** # Pins with no good access point on Grid (V&H) = 5 ( 0%)& E3 U) o$ i- ]' }1 R+ V% _' ]! i
** # Pins with no good access point on Ver-Grid = 5 ( 0%)- Z( @4 D* W, R( y7 E
3 v6 R" M) Z- |/ |' \
若是代表有錯誤的話是否要 Fix 呢? |
|