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某半導體大廠徵求Project Leader , @$ w3 @* M9 j; n! P
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Title Responsibilities:
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! a6 f, _ L( a$ ^7 |3 M. n2 ^1. Coordination among CIS integration, module and product for next generation technology development - K3 Z1 E: [& Q1 S
2. Responsible for WAT analysis and pixel performance characterization. & S7 V) s% j" s# U! H$ ~$ o
3. Experiment design to optimize pixel performance and establishment in process baseline. 9 d G* X4 L5 b( j- Z2 p3 z
+ |) F( ^) Y) z+ {Requirements:
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/ p7 z9 V7 O9 T2 Y! Z2 J) `9 O1. Minimum bachelor degree in Electronics Engineering or related fields.1 Z5 {4 V. w) b: H
2. Minimum 6 years of experiences in Memory product (DRAM, SRAM, CIS, NVP) x2 J3 e% a) |7 [( f
3. Candidate with integration experience are preferred.7 Z4 z$ K0 a e, o/ S/ c, L& a
4. Fluent in English.
. E2 M9 Z1 l- _) L( c+ n1 `! _5. Work location in Tainan, Taiwan.* a# o9 n& D2 R2 w, }
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Package: around annual NT 300萬 ~700萬/ P5 z& z% j' W& O7 l. `" p
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Stock:providing stock option depends on experience0 ^+ |$ K6 A6 \- W' p m
1 q" a% h$ R3 l9 {9 N意者請與 chip123@chip123.com.tw 聯絡! |
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