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AMD Geode LX 800@0.9W處理器
General Features
9 @; z! ~( f b7 D, s■ Functional blocks include:: @! z9 @4 _3 F! c. M
— CPU Core
: A+ H. J& [" W9 }4 s: h5 T" ]— GeodeLink™ Control Processor9 R- B: A& a# K) ~/ h, ~( w
— GeodeLink Interface Units
# D* h5 S- _4 d) d, N& W— GeodeLink Memory Controller$ |7 V' |! } p! j- C$ `' @
— Graphics Processor4 D/ H: V1 f5 Y) N) m2 T) H
— Display Controller* J3 W) O# H& o
— Video Processor" B& Z7 D" x( H; ~8 i7 k0 [& F% h
– TFT Controller/Video Output Port9 _( A' H( C+ z
— Video Input Port
, s) C4 J+ H6 B2 I— GeodeLink PCI Bridge. }( i& n& @+ g4 |. c) w
— Security Block
- G0 D$ X: g0 O5 b# W8 m2 X* {( m■ 0.13 micron process M5 A( n) f( G/ G; H! P
■ Packaging:
1 d% Q5 x2 i7 T! a2 d— 481-Terminal BGU (Ball Grid Array Cavity Up) with
( v% ~% U1 A* h( r) k$ M @3 Jinternal heatspreader5 q- q! K5 Y- O
■ Single packaging option supports all features
& f7 e- ~" C. p W9 e1 y L& w1 G& oCPU Processor Features
, F: {6 f* V) u w+ P, }! |■ x86/x87-compatible CPU core
& D8 q- l4 I/ D9 i7 J8 s■ Performance:
* U" R2 m7 t/ x9 K! I— Processor frequency: up to 500 MHz. Y) {" k' i+ K8 J. O! Q X
— Dhrystone 2.1 MIPs: 150 to 450* y, ^, I& w- U( R, C2 N
— Fully pipelined FPU
! ^3 m; J1 w2 X* Z; W■ Split I/D cache/TLB (Translation Look-aside Buffer):2 w7 O G( E' L+ F$ I6 Z
— 64 KB I-cache/64 KB D-cache2 n7 L6 {0 h% ?% Z% m
— 128 KB L2 cache configurable as I-cache, D-cache,
2 j$ n0 E& x {: Mor both
+ w4 m- f! M, c7 ~9 E v+ V; s■ Efficient prefetch and branch prediction2 i4 n- S2 L A U- S; k% j
■ Integrated FPU that supports the MMX® and
" U1 ~- W& m, i4 x2 l- q( z* M( A' uAMD 3DNow!™ instruction sets
) U% N/ {, n1 K$ d' [5 Z■ Fully pipelined single precision FPU hardware with
+ l5 T& q' f* G, Hmicrocode support for higher precisions; M' {8 v! L5 A: x! @' S
GeodeLink™ Control Processor& y. K1 K; c/ {. W$ c! B
■ JTAG interface:9 e+ S9 A" h! y
— ATPG, Full Scan, BIST on all arrays
' W+ O5 A: B. f) D! ] R: }— 1149.1 Boundary Scan compliant, u: H0 E/ U( ]# R
■ ICE (in-circuit emulator) interface
( t2 H+ g K+ R5 _■ Reset and clock control/ m, D2 j0 ?6 ~- ^& u' |
■ Designed for improved software debug methods and
/ Z: N$ t1 z/ K5 s: F5 v' Rperformance analysis. X; n4 ^' }; b4 W+ q9 q
■ Power Management:
6 X' j# {2 c$ |; {5 ^7 z— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
& g; Z+ I# g# ~500 MHz max power
1 Z( |/ S; w+ m7 \8 D: M0 U— GeodeLink active hardware power management
% `# K Y2 M5 b k4 G— Hardware support for standard ACPI software power6 ?9 e; a1 f7 T! M
management
( ~; A" z1 L4 f— I/O companion SUSP/SUSPA power controls
* @* E5 r; [- F( ~6 s— Lower power I/O& o1 f- a' D2 @5 o2 N
— Wakeup on SMI/INTR9 ? ~% k" M: i& b: ]3 @
■ Designed to work in conjunction with the4 q" W; x/ y9 i- ]9 \/ S
AMD Geode™ CS5536 companion device
7 N9 g) _8 f5 pGeodeLink™ Architecture
- i8 P) V0 b) ]. N/ v2 H- r* h■ High bandwidth packetized uni-directional bus for( g/ y! s# Y% @( v, k) w' g/ J2 }
internal peripherals
. I1 T9 m8 p5 `8 G+ F■ Standardized protocol to allow variants of products to be
; d, |0 `2 S+ |0 {3 M* Ldeveloped by adding or removing modules
7 p( v' i$ n( n8 a4 Q; w4 Y■ GeodeLink Control Processor (GLCP) for diagnostics' k0 A9 d, n; c- T' z T
and scan control
! g. m) p) N( H' ~/ }$ w! g■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
( ]* m5 R# ~9 `& ?+ QGeodeLink™ Memory Controller/ |/ j; j/ n( {3 b% `" }5 U
■ Integrated memory controller for low latency to CPU and9 N9 d! i% e( b& j7 j0 g/ {
on-chip peripherals
( p! L1 U9 N& V& R6 b■ 64-bit wide DDR SDRAM bus operating frequency:
+ m6 p% X/ L8 D' f% {— 200 MHz, 400 MT/S2 k# S* t. \7 b: N
■ Supports unbuffered DDR DIMMS using up to 1 GB
( S u" |+ L/ L6 k8 XDRAM technology
y( R) Z1 n6 j7 c. s$ J■ Supports up to 2 DIMMS (16 devices max)" K1 } e; X8 m, Q
2D Graphics Processor2 f2 u! c' X6 |
■ High performance 2D graphics controller( d5 V# A; z C" G0 M9 }3 i
■ Alpha BLT
- i, Z. [' E. R3 Q5 m2 v0 ~■ Microsoft® Windows® GDI GUI acceleration:
) Y! ?# w( L- H* x3 i" z8 `8 m— Hardware support for all Microsoft RDP codes
! c; q2 V5 S; S■ Command buffer interface for asynchronous BLTs
" x2 N$ l r( ]( b7 [■ Second pattern channel support1 c$ n8 h; K7 A
■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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