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AMD Geode LX 800@0.9W處理器
General Features
. l _! c! z' P$ D) _■ Functional blocks include:
( y I4 P0 `: w f& R! h' E— CPU Core4 E$ }0 c" C4 f' P l* U6 t: |$ w) E' ?
— GeodeLink™ Control Processor
( k$ V6 R4 N/ N— GeodeLink Interface Units4 K% {0 i- ?7 s' o M% U
— GeodeLink Memory Controller
- \. S& c% |/ f! N3 |, ^- U/ F5 p— Graphics Processor5 X0 g5 U& ?$ K0 I$ C
— Display Controller$ r0 [5 y/ j1 [( f) c$ U
— Video Processor
" X# n+ _* G1 L6 L2 v– TFT Controller/Video Output Port
9 P0 |* ~/ T* S6 c— Video Input Port
) i. V0 ^9 L% S( `, f, u/ J& a— GeodeLink PCI Bridge
$ K7 H0 J, i. e6 W9 g8 ^. q" x— Security Block
# {# x4 x& i: v. m9 E■ 0.13 micron process& |( E2 c. a& Q! M1 d
■ Packaging:
! j: `8 `9 n0 y+ |! @— 481-Terminal BGU (Ball Grid Array Cavity Up) with
M) L6 j i, H+ n" @) f7 i# M$ d# uinternal heatspreader: v% e3 M5 o) d, E( P
■ Single packaging option supports all features
; n* [4 _. ?7 P9 m, qCPU Processor Features7 j4 H' \+ R y8 I; E* }
■ x86/x87-compatible CPU core
# m8 I3 b5 ?* J: m3 X■ Performance:$ S* |+ o1 c4 C( p3 B& |
— Processor frequency: up to 500 MHz
4 l9 L! j3 R4 l r$ a3 ]( e, q/ [— Dhrystone 2.1 MIPs: 150 to 450
: O. o/ \5 `% `% X— Fully pipelined FPU' S( w% K3 s/ K' M8 f5 V' {
■ Split I/D cache/TLB (Translation Look-aside Buffer):
- _. l/ d# _3 q* W; ~— 64 KB I-cache/64 KB D-cache
& N$ }/ m/ ~. ?' w— 128 KB L2 cache configurable as I-cache, D-cache,* t7 D2 u& l1 Q
or both
1 e4 d3 K ]) E- _, J% j+ `■ Efficient prefetch and branch prediction! w8 O* {" h/ o7 P4 r
■ Integrated FPU that supports the MMX® and- }. |& r g' }5 |9 r) a6 C# h
AMD 3DNow!™ instruction sets/ F% O: f' s( j
■ Fully pipelined single precision FPU hardware with, h# a0 R! Z1 O
microcode support for higher precisions( I% A% Q" ?" h4 ]6 P2 m
GeodeLink™ Control Processor
5 ~3 ~" J7 l2 X, y: ~■ JTAG interface:
+ t) h2 y$ \1 F- F0 C— ATPG, Full Scan, BIST on all arrays+ m+ I# n; B) `) h, p
— 1149.1 Boundary Scan compliant
- z5 ?3 Y' z, k+ w; U7 {2 l■ ICE (in-circuit emulator) interface
2 S7 T3 u- U$ v7 _/ E$ B5 d■ Reset and clock control' t, Y8 O) |: u
■ Designed for improved software debug methods and
# }' F w2 d9 M! h! O8 Kperformance analysis; a0 @1 ~! o7 c7 h
■ Power Management:" D0 h6 }* Y3 [* k; u& f3 q- k
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @0 s4 a! q+ J0 {( _9 j, S, d& v) v
500 MHz max power1 H1 s/ q$ d9 ^3 t7 u/ @
— GeodeLink active hardware power management
5 N' L Y" ? Y6 m- q) z— Hardware support for standard ACPI software power
$ [$ k5 u$ F& o# W n! n9 A# mmanagement
' W- p2 v' m" m( H2 P2 O- P. S3 a— I/O companion SUSP/SUSPA power controls
3 t; d4 y2 T Y8 Y8 J9 U2 _— Lower power I/O
+ u% @9 @; G9 u' g8 z— Wakeup on SMI/INTR
6 g! \% w4 @$ |5 ]5 A■ Designed to work in conjunction with the
4 y0 O! o7 W0 N7 R" |" eAMD Geode™ CS5536 companion device
0 [ q$ a) k/ d+ WGeodeLink™ Architecture
# x8 l! l4 x. P6 l& n■ High bandwidth packetized uni-directional bus for: R9 G9 W9 W/ O+ \$ L. X% k
internal peripherals; o& `: N1 ~+ r+ S j
■ Standardized protocol to allow variants of products to be" {& R2 g- j7 }/ T& u! n- I d
developed by adding or removing modules
* T5 d2 v, Q7 f* p■ GeodeLink Control Processor (GLCP) for diagnostics
1 H/ R& Y) A' R2 R( U( `2 qand scan control
1 g* y7 w4 B5 a5 ]* n4 c■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
+ @# Z! w# ~5 N% vGeodeLink™ Memory Controller
& H! {$ @0 Q }- ]& Q S■ Integrated memory controller for low latency to CPU and
* |! b. [" `& N5 won-chip peripherals
7 _( ~3 t5 A- }0 ?/ q9 y, X■ 64-bit wide DDR SDRAM bus operating frequency:$ b. q- v9 U: C* {- I) v( d
— 200 MHz, 400 MT/S* U H! B3 a5 s! G
■ Supports unbuffered DDR DIMMS using up to 1 GB# @7 n, V. O w3 P" }: V
DRAM technology
8 _/ C6 g: j9 V6 |■ Supports up to 2 DIMMS (16 devices max)
6 }* [* a O7 ~8 d' ]) i2D Graphics Processor) V l G. |1 g, C, L9 a! O" o, t r" U
■ High performance 2D graphics controller' D$ H1 d( d- L# i, G' M
■ Alpha BLT
! V) J2 q. s- \6 P. U$ [8 w# S9 j( }■ Microsoft® Windows® GDI GUI acceleration:6 G$ g0 x7 l5 ]/ N- h
— Hardware support for all Microsoft RDP codes/ P9 y; v- N4 w; C9 E5 N- m
■ Command buffer interface for asynchronous BLTs
7 g5 x- O0 m9 W% r }■ Second pattern channel support% P! ~2 W( {8 U' g$ ?
■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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