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0. Check circuit topology and connectivity.
2 A: E$ N! {; Z% C* VThis item is the same as item 0 in the DC analysis." D4 e4 ]$ K- G" o) g7 r
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1. Set RELTOL=.01 in the .OPTIONS statement.
3 H- g1 D7 H- p, l! ?0 sExample: .OPTIONS RELTOL=.012 V F5 l6 S; s0 S/ x; ~6 L# _
+ X( M% m2 K6 S3 N9 l D. q2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.- m5 _) y0 H2 g: Z
Example: . OPTION ABSTOL=1N VNTOL=1M$ E9 g# m4 U* Y p9 \$ m
! m+ e" B D/ ^* R# n0 o' D# p1 e, P3. Set ITL4=500 in the .OPTIONS statement.3 {) l: v! K2 F
Example: .OPTIONS ITL4=500( ?# b, P8 N0 d7 j" ~1 \
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.1 B2 l+ C, q6 R" a- ~% Z
- C% ^4 c- l7 X5. Reduce the rise/fall times of the PULSE sources.' E) d& f4 g; J6 {! }
Example: VCC 1 0 PULSE 0 1 0 0 02 J8 \& X" x5 i9 M0 j) k
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.& M, ]& b* ]* I
Example: .OPTIONS RAMPTIME=10NS; R2 o9 V5 w/ b* B ~" z
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
2 w w! K" x$ Z& RExample: .TRAN .1N 100N UIC" j! n7 q$ c- Y/ q
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8. Change the integration method to Gear (See also Special Cases below).
' F# r$ S/ P% N" h8 D! PExample: .OPTIONS METHOD=GEAR |
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