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0. Check circuit topology and connectivity.
3 f8 h; Q/ L" r& }% sThis item is the same as item 0 in the DC analysis.
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" v+ t7 S; V" ?9 t. Q1. Set RELTOL=.01 in the .OPTIONS statement.% J$ A' o' c, E A
Example: .OPTIONS RELTOL=.01+ o8 b" q0 o0 W! u* a# y
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
/ u/ |7 |1 \) a, MExample: . OPTION ABSTOL=1N VNTOL=1M) D8 N7 q" d h( U' e$ n
, c3 b3 |2 E6 {' P( ~3. Set ITL4=500 in the .OPTIONS statement." J# X1 X& x* o
Example: .OPTIONS ITL4=500
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.+ {. @) O$ q9 M9 H9 f" u' F. g: b
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5. Reduce the rise/fall times of the PULSE sources. P! u& k! P: W5 {- V. s' e( A
Example: VCC 1 0 PULSE 0 1 0 0 0 P0 c/ l6 {2 r( y6 Y. z3 j
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.# d. N+ p: S1 V
Example: .OPTIONS RAMPTIME=10NS
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. B9 P+ E6 U# l9 E) \7. Add UIC (Use Initial Conditions) to the .TRAN line., ]( ?9 M, d- I; v2 ]* {5 _$ ]
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).' W( h1 ~8 k% V1 t
Example: .OPTIONS METHOD=GEAR |
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