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0. Check circuit topology and connectivity.
+ W& o$ |+ B L) C CThis item is the same as item 0 in the DC analysis.* y: p! h' W. X1 X4 `# j4 D
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1. Set RELTOL=.01 in the .OPTIONS statement.
- h4 g4 ^5 J! B# \" \6 H! s4 WExample: .OPTIONS RELTOL=.01
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+ j2 p! m7 i/ V3 v/ x2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.1 j6 Q, K) h7 r9 A9 e7 T3 [
Example: . OPTION ABSTOL=1N VNTOL=1M. d+ \( U' y' K$ I: s, H
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3. Set ITL4=500 in the .OPTIONS statement.
8 x: F: }) i' w* cExample: .OPTIONS ITL4=500$ H3 z, v+ c8 a
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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$ S$ b. ]$ m% A8 b, a- t5. Reduce the rise/fall times of the PULSE sources.
0 p/ e5 {. v0 U2 k4 K$ TExample: VCC 1 0 PULSE 0 1 0 0 0
( i r8 h7 a5 |3 ~, F1 cbecomes VCC 1 0 PULSE 0 1 0 1U 1U" y i k1 g# z g
1 T) w+ `8 A n, a1 X6 n8 b6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.0 M. Q' ]. A2 q, ]
Example: .OPTIONS RAMPTIME=10NS
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5 S, E- A9 F& ~! {7. Add UIC (Use Initial Conditions) to the .TRAN line.5 s7 S8 p1 [7 F( M8 {
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).
7 Y, d/ l) [/ |$ O8 ?7 XExample: .OPTIONS METHOD=GEAR |
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