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0. Check circuit topology and connectivity.
% b: I: X- k5 o- p( w' eThis item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.
, B7 ^5 V4 K: M/ v# H: ]Example: .OPTIONS RELTOL=.01
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8 y; ^7 g# x! O, ]5 Y( A2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
4 A$ i2 E" g6 x: x5 yExample: . OPTION ABSTOL=1N VNTOL=1M, z9 p( t! w0 ~% e" Z; `, |- T G4 C
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3. Set ITL4=500 in the .OPTIONS statement.
2 T8 K2 L$ _2 IExample: .OPTIONS ITL4=500
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.$ R# h- Q; G* Q- a2 Z6 i
# \. Q+ j9 h0 L5. Reduce the rise/fall times of the PULSE sources.
+ Z. v" f. p, L+ G9 AExample: VCC 1 0 PULSE 0 1 0 0 0
1 f& C0 V6 y4 c& a& F; n4 Jbecomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
7 Y, i' l! o# Z" pExample: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
. Z' ~3 K& o. C/ {) |! j q2 GExample: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).
: l0 E% {; n, d6 n0 ?Example: .OPTIONS METHOD=GEAR |
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