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0. Check circuit topology and connectivity. l6 c0 P7 d/ r4 P3 ]* l
This item is the same as item 0 in the DC analysis.
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2 V; E, H/ i& P+ u+ [9 B O1. Set RELTOL=.01 in the .OPTIONS statement.6 L4 U7 W" c% S) B% ^/ R- m- |
Example: .OPTIONS RELTOL=.01- s: _: e. P2 u7 g ]
' k: y) ?! [ a/ F2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
. a, Q; I7 H9 W; q# [: xExample: . OPTION ABSTOL=1N VNTOL=1M
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+ ]/ c' o* j; V3. Set ITL4=500 in the .OPTIONS statement.
h7 j- o+ e/ \" d$ F) L5 ~" {Example: .OPTIONS ITL4=5006 h# J$ ?8 ]) x# E8 e3 k
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance./ @* |1 l; l( \* `- O @3 A! i( C1 B
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5. Reduce the rise/fall times of the PULSE sources.
9 z% t u1 T9 x4 AExample: VCC 1 0 PULSE 0 1 0 0 0
* o7 V. E9 _* I j. P5 L: Obecomes VCC 1 0 PULSE 0 1 0 1U 1U
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9 b5 G% Y* P, n& p6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
, _2 ^) Y% M7 m6 I5 I' L3 \1 HExample: .OPTIONS RAMPTIME=10NS/ Y$ \& \$ f4 W# Q0 ^+ ^3 D
/ v g8 X: {5 F% ^8 z7. Add UIC (Use Initial Conditions) to the .TRAN line.
/ k6 m1 j. s' }3 v& `. KExample: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).
8 J; `4 Q# `. M" P( N8 NExample: .OPTIONS METHOD=GEAR |
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