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0. Check circuit topology and connectivity.4 k! F' y7 t. f1 J
This item is the same as item 0 in the DC analysis.
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5 O! B/ K' M: Y9 j7 ]9 |4 |1. Set RELTOL=.01 in the .OPTIONS statement.
; ?# m8 T2 j7 X9 s. PExample: .OPTIONS RELTOL=.01; H; b4 p. B, V$ n2 B- A, Y
' r x" T! I t5 M6 X2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.. f* `* T p& N R9 ^
Example: . OPTION ABSTOL=1N VNTOL=1M+ A1 T1 a- [& T& N1 ]1 Q7 n' u
& \7 l6 x) f+ m8 U3. Set ITL4=500 in the .OPTIONS statement.
+ C" @) g2 W: W+ y: L1 cExample: .OPTIONS ITL4=500! _6 c& r7 q! F: A* l. |
d/ Y5 V8 e& f Y4 u4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance." f( F$ p, _! T
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5. Reduce the rise/fall times of the PULSE sources.' [4 U0 W, A$ a% O# _
Example: VCC 1 0 PULSE 0 1 0 0 08 O, i K, w/ f4 G
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.( D$ j. h1 a8 l. C0 T$ m
Example: .OPTIONS RAMPTIME=10NS$ I; x, \4 o! t7 L
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
8 Z A7 l2 j0 ?# B# ?Example: .TRAN .1N 100N UIC6 w, K$ L# I! s7 y& F. B
$ P' u% l7 z0 n" e: ~; {8. Change the integration method to Gear (See also Special Cases below).4 b( ~9 P) ~+ m- r n( ~. b" T
Example: .OPTIONS METHOD=GEAR |
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