You must be sure that, 3 @$ V/ Q, t8 U+ f7 E1. your design output meets standard SVGA HSYNC/VYNC timing5 ^+ k! s% [, \. g4 ~
2. You must also set constraint on the ISE project, and check the timing report after 3 U# G( T3 }8 k4 i* E8 ^# [1 w
the P&R is done. (also called STA timing report)3 z8 G2 r$ h" y. w* c8 l
3. Sometimes, you must check the board, and I/O SSO issue(signal integrity....)