ASIC設計工程師如何保住飯碗？

innoing123

Junior Physical Design Engineer
7 k: @! f- i/ O公      司：A famous IC company
工作地点：北京
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Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
4 l9 l. w/ Y2 J; `0 X$ X0 r2 m8 Q+ q        Complete third party IP integration and ensure vendor guidelines are followed.
$ w+ L; D4 q. L+ V( D        Responsible for physical verification (DRC/LVS).
8 [' c# P9 k7 \/ t        IO ring design, fullchip floorplan.
/ V( _- ]* G% a, }4 Q        Block level implementation.
3 t; Q2 z3 g. u0 S, B        Work with front-end engineers to resolve problems and achieve design closure.
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3 P. w7 |2 [4 P. j# f6 R3 ]Candidate Qualifications:
Candidate must:
        Hold BSEE (MS preferred).
, E, S& ^1 z0 \        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
2 [  G8 G# J5 m4 Y9 Z5 q9 m        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
        Have the ability to independently identify and resolve design, tool, and flow problems.
        Have related timing and physical concept.
        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
        Familiar with EDA tools.
' S+ i4 Q- W6 m9 }8 p. u        Familiar with Linux environments.  

Any of the following is beneficial:
        STA constraint design
$ v  v% i  M; c& m* l7 A, J       Equivalence checking ?RTL to gates, and gates to gates.