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Senior Digital Design Engineer( v) V, {5 Y0 @ S0 I
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公 司:A leading semiconductor company% G4 c j1 R* |
工作地点:香港
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f- s' ~8 R5 Q5 ]Job Responsibilities:
7 v8 w2 P8 {3 O. V9 }; F Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
' M- D: ]* ?3 ~1 Y" W Develop verification environment and coverage closure
6 m% f* y2 F% }# k- j; ? Support wafer level testing and silicon evaluation
6 k: Q: ] |* T/ P! }" J Prepare technical documents
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+ W, h; @& A, T, PJob Requirements: % w' {' l0 ~' l6 n, W v( L7 B8 z
B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage; {2 _; B; u1 e# q
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations # m7 J+ @; W+ ^% }) l' c) {
Knowledge of SoC and embedded system. $ Y/ J: E! x5 G/ c+ ]( i
Knowledge of scripting languages such as Perl, TCL and Make , L- B1 F" k9 @+ Z4 Z9 N% j* @, e: N
Candidate with less experience will be considered as Digital Design Engineer |
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