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Sr. ASIC Design Engineer (encoder/decoder)
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1 V# m* L0 l1 p9 j! M公 司:a leading developer of advanced digital imaging solution. d% h+ P1 C) C0 O* O+ S2 t
工作地点:上海, K) e8 d% {2 s6 x* Y/ }
: y" q$ M; Y& N$ N6 U" s7 cPosition Overview: The candidate will join a team of highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.
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主要职责 (70%)
8 a, ~8 A* A/ `3 }2 I2 {: F7 BIn-depth knowledge of TV encoder and decoder design. Good understanding of TV system design. ! t" |3 ^1 d# C2 U" _( z7 y0 J5 i
Proficiency on digital filter algorithms and hardware implementation. 4 B3 f/ g9 e, E
Development and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing.
; a1 o/ P$ @8 L& x8 zParticipate in the FPGA platform development and lab debugging 3 J1 z" W- h* Q4 z$ ^* p
1 i- d7 D. Q* F. ~: `: a! u. X) h其他职责 (30%)
4 Q2 U8 T- [) MParticipate in block level architecture design Assisting embedded FW development.
# ~* {4 y2 T. u" W职位要求
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: ]: m+ s8 v5 K; b经验/技能
# K0 n7 B7 ?; F& e: F1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus * i7 X6 [/ d! a. i, ^
2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications. 1 r, \% L. ]+ E. I, d: _, J* j
3. Good communication skills, especially in technical writing and reporting; 1 }; {0 \$ J/ M, ]' [
4. Self-motivated and ability to excel in a team environment.
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MSEE/CE with 3+ years of industry experience |
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