ASIC設計工程師如何保住飯碗？

ranica

资深数字IC设计工程师（图形图像方向）
! p) o* H1 |" u- Y+ U公      司：A famous IC company
工作地点：上海

岗位职责：(图形图象处理和视频编解码方向)：
1、根据市场需求和芯片定位，参与并带领团队完成图形图像处理或视频编解码等复杂IP的设计验证和交付；
1 O  @4 F4 x. t2 Q8 M$ @2、对项目进度和质量负责，组织具体技术难点或紧急任务的讨论和攻关，协调其他团队共同完成SPEC的制定和收敛；
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5 I$ }/ |) K1 d4 b岗位要求：
1、硕士及以上学历，电子、通信、计算机或微电子专业；
$ F7 z2 k, I2 M9 m4 ], C2、有至少两年以上图形图像或视频编解码等领域的IP设计经验；
3、具备丰富的图形图像处理或视频编解码等相关领域的系统知识
  T6 }3 \" U& R: |  l4、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程；
5、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
  a- r2 e0 b6 o1 E  s! ~6、有团队管理经验者优先考虑；

ranica

数字IC设计工程师
公      司：A famous IC company
工作地点：上海

1 {8 E4 o" ~! M! I3 l* Y% T) S岗位职责：
负责各种IP（图形图像接口、图形图象处理、视频编解码、DDR存储接口、Flash接口、USB接口等）的设计、时钟复位模块的设计或者SOC相关的集成设计、系统设计、架构设计。
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职位要求：
1、硕士及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog等语言的编程，有扎实的数字电路基础；
3、有1~2年的相关工作经验；
$ Z7 r3 T( j* U9 J7 o* U* u4、具有较强的学习能力、沟通能力和良好的团队合作精神；
9 S. _: K3 E8 o5、在以下相关的模块或接口（其中之一）有一定的工作经验：图形图像接口、图形图象处理、视频编解码、DDR存储接口、 Flash接口、USB接口等
; P9 |' S2 o* d6、有大型SOC芯片的研发经验者优先考虑。

ranica

Sr. Staff to Principal Engineer/Mgr
公      司：A famous IC company
工作地点：上海

+ p' r1 r( I  f  S5 E4 MJob description
The candidate will be responsible for the architecture and ASIC design and co-verification of various 802.11 wireless baseband IPs within current and next generation wireless products. The candidate will work within the local DSP/digital development team and closely with system/simulation/verification/RF engineering teams in US to develop and implement DSP/digital blocks to build WiFi IPs.
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8 q& |! q2 Q8 b% ~, D' mJob responsibilities includes: spec development and design of DSP/digital blocks, developing co-verification platforms, performing simulations, and solving integration and testing problems during the development, characterization, and production stages of the product. Successful candidate must have the ability to communicate with engineers of various backgrounds: systems, software, digital hardware, RFIC design, and verification

ranica

职位要求
?Extensive hands-on experience in the development of WiFi baseband IC design. The candidate must have at least 8-years development experience on WiFi 802.11 a/g/b including minimum 3 years on 802.11n/ac.  
/ P# x% V2 T6 k, L  }7 z: p" n( p5 u?Deep knowledge and good understanding of: digital communication theory, information theory; specifically on: equalization, Fourier transform, spatial-temporal coding, linear and maximum-likelihood estimation, Viterbi decoding, frequency/ timing estimation and calibration, automatic gain control, transmitter beam forming, diversity combining, and their high-speed DSP/digital implementation.  
?Extensive experience with RTL programming languages.
/ I% Q' O% B6 C4 {?Experience with verification methodologies and tools and advanced complex RTL/C test-bench developments. The familiarity with UVM environment is a plus.
?Experience with developing algorithms in C, C++, and Mat lab.
?Experience with scripting language such as Perl, Python.
?Must have experience with lab testing and characterization of digital sub-systems.
?Candidate must have strong English communication skills with willingness to interact with various groups within the company.
?Experience with physical design flows, tools, methodologies, and development of timing constraints is a plus.
?Familiarity with flows and tools for co-simulation of RTL and C models is a plus.
7 _- X) H# C4 o( y; ]1 r# }; Y0 z?Familiarity with testing and integration of RF and baseband systems in the lab is a plus.
( ^6 Y  Q: H  G6 p+ C5 s?Experience with implementation of calibration modules for RF/Analog blocks is a plus..
?Typically requires a Master degree and 8 years of experience or a PhD and 5 years, in VLSI/ASIC architecture design or ASIC implementation of digital signal processing function.

ranica

Senior Digital Design Engineer

公      司：A leading semiconductor company
! Z% h- R9 p8 Y) A& O; J工作地点：香港
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1 M6 t' ~7 F  X' d& CJob Responsibilities:
# e2 P" ]- }3 l& ^3 Y6 |% s4 R' ]8 `    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
& _' e/ P. W, h/ j% E: P! Y8 ~  `2 K    Support wafer level testing and silicon evaluation
3 v0 l; c+ m* l1 y% ?$ B7 n0 n$ F    Prepare technical documents

. r9 E7 A, O4 Q" G1 v9 zJob Requirements:
, v+ y8 g1 U& ?! {9 J  r    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
; K+ k, i( w! a    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
    Candidate with less experience will be considered as Digital Design Engineer

ranica

Junior Physical Design Engineer
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# S, H0 ]9 R( W/ O& a; j6 P7 ~( G# C公      司：A famous IC company
1 p  ~, {& S- E9 T" f工作地点：北京

Position Tasks, Duties and Responsibilities
. z, A0 l7 X6 e$ [1 g1 G7 CThe ASIC Physical Design Engineer will:
. h7 ?! ~3 `8 m/ }$ b        Complete third party IP integration and ensure vendor guidelines are followed.
' T$ X+ h' L0 c  @/ v        Responsible for physical verification (DRC/LVS).
        IO ring design, fullchip floorplan.
2 M9 v2 R1 U  y6 o$ ]        Block level implementation.
        Work with front-end engineers to resolve problems and achieve design closure.

6 Q6 `4 B; t* Y0 e, q4 ACandidate Qualifications:
Candidate must:
        Hold BSEE (MS preferred).
% K( m9 n9 H$ v/ l3 b" \' \& F        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
4 l8 R+ V6 i/ U# e( n9 T        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
        Have the ability to independently identify and resolve design, tool, and flow problems.
        Have related timing and physical concept.
# B  X* ^. f, x        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
; ]; a5 M  a& P2 [: Z0 d2 v: T        Familiar with EDA tools.
        Familiar with Linux environments.  
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Any of the following is beneficial:
        STA constraint design
       Equivalence checking ?RTL to gates, and gates to gates.

ranica

Sr. ASIC Design Engineer (encoder/decoder)

公      司：a leading developer of advanced digital imaging solution
1 ?) F8 X' X$ ?, D  O5 K* e6 a7 x工作地点：上海
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Position Overview: The candidate will join a team of  highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.   
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! h6 G: n7 {: E主要职责 (70%)
In-depth knowledge of TV encoder and decoder design. Good understanding of TV system design.  
Proficiency on digital filter algorithms and hardware implementation.
  X1 F: o; O, ~3 ]$ f, L- k* @* Q' gDevelopment and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing.
Participate in the FPGA platform development and lab debugging   

7 E0 ?6 M) n1 U其他职责 (30%)
Participate in block level architecture design Assisting embedded FW development.
# P# S9 z  n& U! }* {9 M3 i1 ^职位要求
3 G% a2 L0 n8 t8 i; D; ~岗位资格
! O5 P7 \( B, s! \" }经验/技能
1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus
2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications.
3. Good communication skills, especially in technical writing and reporting;
! J7 Z+ c& D. U6 M2 w4. Self-motivated and ability to excel in a team environment.   
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教育
6 H6 Y- N' \1 |9 m! V7 SMSEE/CE with 3+ years of industry experience

ranica

数字芯片设计工程师（DFT/综合）
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公      司：A mobile chipset semiconductor company
: w% }- v$ h8 {! d+ C7 c% j1 I7 e工作地点：上海

职位描述：
1、To provide and support SYN&DFT work for several projects in parallel  
1 X9 d- j" m# A; F, ?7 a2、Run block level implementation for each project, include synthesis, DFT and LEC
. {- X3 w9 E# z3、Support block level physical evaluation  
8 @8 r, o/ Y/ b4、co-work with designer and provide block level SDC file
! W) q! `4 k: r. {- H5、co-work with Back-end team for timing signoff
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0 M+ b/ y" p5 h9 L职位需求：
- N3 J- H3 t1 B. \/ G' f; {1. 了解集成电路设计的基本流程
' K. j0 a( |5 |2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
# D  f0 c, ]  ?8 D- ]: d0 l1 [) Y& a3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
8 B3 a% m$ |% B0 R! C3. 具有良好的英语阅读和书写能力。