ASIC設計工程師如何保住飯碗？

ritaliu0604

客户 a start up company with innovative technology
" v4 G+ `, @9 w% V地点 Shanghai
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  s: |4 {# v( ^; G( o; H7 h9 \职位要求
1 R& o4 {- [% j) I8 P! i9 w: g) C5 + years experience in ASIC design -> must
0 H% f) {' X/ z4 U- y· MS in Electrical Engineering (or equivalent) is a must have
· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
. H9 @  g! E& ^# k6 I( d· Experience with interfaces such as SPI, SDIO, USB -> plus
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
- G5 I. x3 R4 P1 y8 s· Must be expert in Verilog RTL language -> must
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
( T6 p$ o! r2 n. W- h/ j7 l: |· FPGA emulation experience -> plus
' H" z, T( K8 z9 ]7 H5 ~, x' |· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
· Experience with digital backend

ritaliu0604

资深变频空调方案研发工程师
! z5 F  _2 K. X4 D0 F
" A& U5 @/ k8 G9 X公      司：A famous IC design company in shanghai
工作地点：上海
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职位描述
1 f  U. R& o) h( L: l2 m從事變頻空調控制軟件的研發。
1 t. {6 L8 X4 O) N& U
0 B6 ~2 h4 }5 h/ d- o$ @职位要求
% ?9 g/ C- ?) G) |有變頻空調控制軟件的研發經驗，熟悉變頻空調控制算法及相關技術

ritaliu0604

数字芯片设计工程师（DFT/综合）
; H2 L  L: e/ {2 z6 {. h) U公      司：A mobile chipset semiconductor company
工作地点：上海

) Y! k- q) E2 R4 U; S( O( x职位描述：
5 Q$ F- I" {# [# K: t3 P! S7 T1、To provide and support SYN&DFT work for several projects in parallel  
2、Run block level implementation for each project, include synthesis, DFT and LEC
! k; ^: _  h) |: {: I. i3、Support block level physical evaluation  
4、co-work with designer and provide block level SDC file
: J- f8 Q. o* s+ N2 {5、co-work with Back-end team for timing signoff

# z) L! B8 W0 b3 A职位需求：
1. 了解集成电路设计的基本流程
- o: H% N& c4 G0 O. f2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
) v: J: y) e) @6 ?% }3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。