|
Junior Physical Design Engineer
0 N7 t1 S. n/ R$ [0 B2 l- z! n/ h2 [+ e2 p6 O* l& R
公 司: famous IC company. P% H" ^3 t j. P( _1 k. ?
工作地点:北京
- L: l y) l5 r9 c% A8 \' x! \
- B0 h& L7 O' N, RPosition Tasks, Duties and Responsibilities & t% |( n# ?* a
The ASIC Physical Design Engineer will:
# E3 r3 S$ T) v Complete third party IP integration and ensure vendor guidelines are followed.
L% g0 R; V# W1 E Responsible for physical verification (DRC/LVS). " n' G4 G% N x# T7 c* I# r* I) V
IO ring design, fullchip floorplan. / R3 E$ M! v- J; a
Block level implementation. , w8 v! Q1 V: ], m% b: B
Work with front-end engineers to resolve problems and achieve design closure.
4 u6 z9 r7 {& C& [* T: _/ t3 Z
- f. u1 `( Q! p2 U* P* h. H% uCandidate Qualifications: # C) ~6 F3 \" W! E! b$ o: U
Candidate must: ( l* J8 B9 s- d: }8 K) a
Hold BSEE (MS preferred).
- j" ]0 t! F0 l% u9 Z+ e, W Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification ' C. V: l( D2 S+ N) c
Be able to complete block and chip level tapeout quality LVS and LVS and DRC. 1 a9 k3 b' _( _) d8 q t( ~" |
Have the ability to independently identify and resolve design, tool, and flow problems.
8 P2 ?. N4 M$ G$ J4 f Have related timing and physical concept.
# l, H3 u$ Q5 \" r Be able to design and implement physical design strategies and methodologies for deep submicron designs.! [! w& {3 a/ \% P/ Q H
Familiar with EDA tools. 2 |7 w6 f& N) x J7 Q- O. ^; X
Familiar with Linux environments.
4 p2 m* F0 o) a! j
8 m" K2 K: S/ u! `$ O" {1 L' x2 f" CAny of the following is beneficial:
J$ L0 D, v% e STA constraint design
6 U5 Q+ G' R( O2 h! @ Equivalence checking ?RTL to gates, and gates to gates. |
|